# US 2022/0285293 A1 · Integrated system-in-package with radiation shielding

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- Number: US 2022/0285293 A1
- Document ID: US20220285293A1
- Status: Published application
- Kind: A1
- Application number: 17/752,037
- Filed: 2022-05-24
- Published: 2022-09-08
- Earliest claimed: 2020-04-16
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Vivek Swaminathan Sridharan; Yiqi Tang; Christopher Daniel Manack; Rajen Manicon Murugan; Liang Wan; Hiep Xuan Nguyen
- Web page: https://patentgrep.com/patent/US20220285293A1

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10H 20/01: Manufacture or treatment
- H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/465: {Bumps or wires}
- H10W 70/635: {Through-vias}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/30: Die-attach connectors
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/811: {Multiple chips on leadframes}
- H10H 20/0362: {of encapsulations}
- H10H 20/0364: {of interconnections}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/695: Organic materials
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

## Claims

### Claim at position 1

1-12. (canceled)

### Claim 13

A method of forming a system in a package (SIP), comprising:
providing carrier layer regions that comprises a dielectric material with at least one metal post through a thickness of the carrier layer region, adjacent ones of the carrier layer regions defining a gap having dimensions sufficient for placement of a driver integrated circuit (IC) die within the gap;
positioning the driver IC die within the gap, the driver IC die comprising a substrate having circuitry configured for a function with nodes connected to bond pads exposed by openings in a top side of a first passivation layer, wherein the driver IC die is positioned with the bond pads facing up;
forming a dielectric layer on the first passivation layer and on the carrier layer regions including filled vias therethrough coupled to the bond pads and to the metal post;
forming a light blocking layer on sidewalls and on a bottom side of the substrate having a thermal conductivity at 20° C. of at least 10 W/m·K, and
flipchip mounting a first device including a light emitter for emitting light at a wavelength having first bondable features to a first portion of the bond pads, wherein the flipchip mounting comprises forming a solder connection.

### Claim 14 (depends on 13)

The method of claim 13, wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K and blocks at least 90% of the light that is incident thereon.

### Claim 15 (depends on 13)

The method of claim 13, further comprising flipchip mounting a second device having second bondable features positioned lateral to the first device to a second portion of the bond pads.

### Claim 16 (depends on 13)

The method of claim 13, further comprising forming a second passivation layer on the first passivation layer, and adding an additional light blocking passivation layer that comprises a buildup layer on a top side and on a bottom side of the SIP.

### Claim 17 (depends on 13)

The method of claim 13, further comprising dispensing a light blocking adhesive layer on the first passivation layer and forming a second passivation layer on the light blocking adhesive layer.

### Claim 18 (depends on 13)

The method of claim 13, further comprising forming a layer of backside metal on a back side of the driver IC die.

### Claim 19 (depends on 13)

The method of claim 13, wherein the second device comprises a resistor, capacitor, or an inductor.

### Claim 20 (depends on 13)

The method of claim 13, wherein the light emitter comprises a semiconductor laser or a light-emitting diode (LED), and wherein the wavelength is 500 nm to 2000 nm.

### Claim 21 (depends on 13)

The method of claim 13, wherein the light blocking layer comprises a metal, a metal alloy, or a polymer including carbon loading at a loading level of at least 1 weight %.

### Claim 22 (depends on 13)

The method of claim 13, further comprising forming the gap using laser drilling.

### Claim 23 (depends on 13)

The method of claim 13, further comprising forming metal pillars on the bond pads.

### Claim 24 (depends on 13)

The method of claim 13, wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K

### Claim 25

A method of forming a system in a package (SIP), comprising:
providing carrier layer regions comprising a dielectric material with at least one metal post therethrough, adjacent ones of the carrier layer regions defining a gap having dimensions sufficient for placement of a driver integrated circuit (IC) die within the gap;
positioning the driver IC die within the gap, the driver IC die comprising a substrate having circuitry configured for a function with nodes connected to bond pads exposed by openings in a top side of a first passivation layer, wherein the driver IC die is positioned with the bond pads facing up;
forming a dielectric layer on the first passivation layer and on the carrier layer region including filled vias therethrough coupled to the bond pads and to the metal post;
forming a light blocking layer on sidewalls and on a bottom side of the substrate;
providing a first device including a light emitter for emitting light at a wavelength having first bondable features thereon; and
connecting the first bondable features to the bond pads.

### Claim 26 (depends on 25)

The method of claim 25, wherein the light blocking layer has a thermal conductivity at 20° C. of at least 10 W/m·K and blocks at least 90% of the light that is incident thereon.

### Claim 27 (depends on 25)

The method of claim 25,
further comprising positioning a second device having second bondable features lateral to the first device,
wherein the second bondable features are connected to the second portion of the bond pads.

### Claim 28 (depends on 25)

The method of claim 25, further comprising forming a second passivation layer on the first passivation layer, and an additional light blocking passivation layer on the second passivation layer.

### Claim 29 (depends on 25)

The method of claim 25, further comprising forming a light blocking adhesive layer on the first passivation layer and a second passivation layer on the light blocking adhesive layer.

### Claim 30 (depends on 25)

The method of claim 25, further comprising forming a layer of backside metal on a back side of the driver IC die.

### Claim 31 (depends on 26)

The method of claim 26, wherein the second device comprises a resistor, capacitor, or an inductor.

### Claim 32 (depends on 25)

The method of claim 25, wherein the light emitter comprises a semiconductor laser or a light-emitting diode (LED), and wherein the wavelength is 500 nm to 2000 nm.

### Claim 33 (depends on 25)

The method of claim 25, wherein the light blocking layer comprises a metal, a metal alloy, or a polymer including carbon loading at a loading level of at least 1 weight %.

### Claim 34 (depends on 25)

The method of claim 25, wherein the dielectric layer includes carbon loading at a loading level of at least 1 weight % for light blocking.

### Claim 35

A method of forming a system in a package (SIP), comprising:
providing a leadframe including a die pad and a plurality of leads or lead terminals, where the die pad and the leads or lead terminals are separated by a mold compound;
placing a driver integrated circuit (IC) die on the die pad comprising a substrate having circuitry configured for a function with nodes connected to a plurality of bond pads including a first bond pad, wherein the driver IC die is positioned on the die pad with the plurality of bond pads facing up;
placing a patterned redistribution layer (RDL) over a top side of the driver IC die;
forming a mold compound on sides of the driver IC die having metal posts throughout its thickness attached to the leads or the lead terminals;
wherein the RDL includes a first portion over the first bond pad, and traces between some of the plurality of bond pads and the metal posts;
attaching a first device including a light emitter for emitting light at a wavelength to first bondable features on the first portion of the RDL; and
wherein the RDL blocks at least 90% of the light that is incident thereon.