# US 2022/0285290 A1 · Package substrate and semiconductor package including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285290 A1 - Document ID: US20220285290A1 - Status: Published application - Kind: A1 - Application number: 17/750,903 - Filed: 2022-05-23 - Published: 2022-09-08 - Earliest claimed: 2019-08-12 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Byungwook KIM; Ayoung KIM; Seongwon JEONG; Sangsu HA - Web page: https://patentgrep.com/patent/US20220285290A1 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/68: Shapes or dispositions thereof - H10W 70/6875: {being on a metallic substrate, e.g. insulated metal substrates [IMS]} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/073: {of die-attach connectors} - H10W 72/29: Bond pads specially adapted therefor - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads. ## Claims ### Claim 1 A package substrate comprising: an insulation substrate; a conductive layer provided in the insulation substrate; upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer; lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer; and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads, wherein the at least one trench has an arc shape in at least one row, a plurality of dots shape, or a zigzag shape that partially surround each of the upper pads. ### Claim 2 (depends on 1) The package substrate of claim 1, wherein the at least one trench is provided in a direction crossing a direction from a central portion of the insulation substrate to a corner of the insulation substrate. ### Claim 3 (depends on 2) The package substrate of claim 2, wherein the upper pads comprise corner pads provided at corners of the insulation substrate, and wherein the at least one trench partially surrounds each of the corner pads. ### Claim 4 (depends on 2) The package substrate of claim 2, wherein the upper pads comprise edge pads provided at an edge portion of the insulation substrate, the edge portion of the insulation substrate being provided between corners of the insulation substrate and the central portion of the insulation substrate, and wherein the at least one trench partially surrounds each of the edge pads. ### Claim 5 (depends on 2) The package substrate of claim 2, wherein the at least one trench comprises: a first trench partially surrounding a first pad among the upper pads provided in a first region, the first region being defined by a first radius from a center of the insulation substrate, and the first trench having a first width; a second trench partially surrounding a second pad among the upper pads in a second region, the second region being defined by a second radius longer than the first radius from the center of the insulation substrate to surround the first region, and the second trench having a second width wider than the first width; and a third trench partially surrounding a third pad among the upper pads in a third region, the third region being defined by a third radius longer than the second radius from the center of the insulation substrate to surround the second region, and the third trench having a third width wider than the second width. ### Claim 6 (depends on 1) The package substrate of claim 1, wherein a depth of the at least one trench is less than a depth of the insulation substrate. ### Claim 7 (depends on 6) The package substrate of claim 6, wherein the depth of the at least one trench is greater than or equal to 5% of the depth of the insulation substrate. ### Claim 8 (depends on 1) The package substrate of claim 1, wherein a depth of the at least one trench is equal to a depth of the insulation substrate. ### Claim 9 (depends on 1) The package substrate of claim 1, wherein the at least one trench is provided on at least one of the upper surface of the insulation substrate and the lower surface of the insulation substrate. ### Claim 10 A package substrate comprising: an insulation substrate; a conductive layer provided in the insulation substrate; upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer; lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer; and trenches provided at portions of the insulation substrate adjacent to corner pads among the upper pads, the corner pads being provided at corners of the insulation substrate in a direction crossing a direction from a central portion of the insulation substrate to the corners of the insulation substrate, a depth of each of the trenches being from 5% to 100% of a depth of the insulation substrate, wherein at least one of the trenches has an arc shape in at least one row, a plurality of dots shape, or a zigzag shape that partially surround each of the upper pads. ### Claim 11 (depends on 10) The package substrate of claim 10, wherein each of the trenches partially surrounds each of the corner pads, respectively. ### Claim 12 (depends on 11) The package substrate of claim 11, further comprising second trenches provided on a direction toward the corners of the insulation substrate to partially surround at least one of the upper pads except for the corner pads in the direction crossing the direction from the central portion of the insulation substrate to the corners of the insulation substrate, wherein a width of each of the second trenches is less than a width of each of the trenches surrounding each of the corner pads. ### Claim 13 (depends on 12) The package substrate of claim 12, wherein the at least one of the upper pads surrounded by the second trenches is provided adjacent to each of the corner pads. ### Claim 14 (depends on 10) The package substrate of claim 10, wherein a depth of each of the trenches is less than a depth of the insulation substrate. ### Claim 15 (depends on 10) The package substrate of claim 10, wherein the trenches is provided on at least one of the upper surface of the insulation substrate and the lower surface of the insulation substrate. ### Claim 16 A semiconductor package comprising: a semiconductor chip comprising bump pads; conductive bumps connected to the bump pads, respectively; and a package substrate comprising: an insulation substrate provided under the semiconductor chip, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connecting the conductive layer with the conductive bumps, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads, wherein the at least one trench has an arc shape in at least one row, a plurality of dots shape, or a zigzag shape that partially surround each of the upper pads. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein the at least one trench is provided in a direction crossing a direction from a central portion of the insulation substrate to a corner of the insulation substrate, and wherein the at least one trench partially surrounds each of corner pads provided at each of a corners of the insulation substrate. ### Claim 18 (depends on 16) The semiconductor package of claim 16, further comprising an underfilling layer provided between the semiconductor chip and the package substrate and filling the at least one trench, wherein the underfilling layer has a coefficient of thermal expansion (CTE) lower than a CTE of the package substrate.