# US 2022/0285286 A1 · Package comprising metal layer configured for electromagnetic interference shield and heat dissipation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285286 A1 - Document ID: US20220285286A1 - Status: Published application - Kind: A1 - Application number: 17/191,550 - Filed: 2021-03-03 - Published: 2022-09-08 - Earliest claimed: 2021-03-03 - Assignees: QUALCOMM Technologies, Inc.; Rf360 Europe GmbH - Applicants: QUALCOMM Technologies Inc.; RF360 Europe GmbH - Inventors: Marc HUESGEN; Philipp Michael JAEGER - Web page: https://patentgrep.com/patent/US20220285286A1 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 40/10: Arrangements for heating - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 40/778: {in encapsulations} - H10W 42/273: {the arrangements being between laterally adjacent chips, e.g. walls between chips} - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 72/50: Bond wires - H10W 74/016: {using moulds} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 44/248: {for antennas} - H10W 70/63: Vias, e.g. via plugs - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A package that includes a substrate, an integrated device coupled to the substrate, an encapsulation layer located over the substrate, at least one encapsulation layer interconnect located in the encapsulation layer, and a metal layer located over the encapsulation layer. The substrate includes at least one dielectric layer and a plurality of interconnects. The encapsulation layer interconnect is coupled to the substrate. The metal layer is configured as an electromagnetic interference (EMI) shield for the package. The metal layer is located over a backside of the integrated device. ## Claims ### Claim 1 A package comprising: a substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate; an encapsulation layer located over the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; and at least one metal layer located over the encapsulation layer, wherein the at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package, and wherein the at least one metal layer is located over a backside of the integrated device. ### Claim 2 (depends on 1) The package of claim 1, wherein the at least one metal layer is configured as a conformal EMI shield for the package, and wherein the at least one encapsulation layer interconnect is configured as a compartmental EMI shield for the package. ### Claim 3 (depends on 1) The package of claim 1, wherein the at least one encapsulation layer interconnect includes at least one through mold via (TMV) and/or at least one wire bond. ### Claim 4 (depends on 3) The package of claim 3, wherein the at least one through mold via (TMV) and/or the at least one wire bond is coupled to the plurality of interconnects of the substrate. ### Claim 5 (depends on 1) The package of claim 1, wherein the package includes a plurality of integrated devices coupled to the substrate. ### Claim 6 (depends on 1) The package of claim 1, wherein the at least one metal layer and the at least one encapsulation layer interconnect is configured to be coupled to ground. ### Claim 7 (depends on 1) The package of claim 1, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 8 (depends on 7) The package of claim 7, wherein a majority of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, and (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 9 (depends on 7) The package of claim 7, wherein at least twenty percent (20%) of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, and (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 10 (depends on 1) The package of claim 1, further comprising a second integrated device coupled to the substrate, wherein the at least one metal layer is located over a backside of the second integrated device, wherein the at least one metal layer is configured as an EMI shield for the integrated device and the second integrated device, wherein the at least one metal layer is configured to be coupled to ground, and wherein the at least one metal layer is further configured to dissipate heat away from the integrated device and the second integrated device. ### Claim 11 (depends on 10) The package of claim 10, wherein the at least one encapsulation layer interconnect comprises: a plurality of through mold vias (TMVs) that at least partially surround the integrated device; and a plurality of wire bonds that at least partially surround the second integrated device. ### Claim 12 (depends on 11) The package of claim 11, wherein the at least one metal layer and the plurality of TMVs are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the metal layer, (iii) the plurality of TMVs, and (iv) a first plurality of interconnects of the substrate, and wherein the at least one metal layer and the plurality of wire bonds are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one metal layer, (iii) the plurality of wire bonds, and (iv) a second plurality of interconnects of the substrate. ### Claim 13 (depends on 10) The package of claim 10, wherein at least twenty percent (20%) of the heat that is generated by the integrated device and the second integrated device is dissipated by heat conduction through (i) the at least one metal layer, (ii) the at least one encapsulation layer interconnect, and (iii) the plurality of interconnects of the substrate. ### Claim 14 (depends on 1) The package of claim 1, wherein the integrated device includes a die, a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, a resistor, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a processor, a memory, a power amplifier, a switch, a system on chip, an integrated circuit device, a MEMS device, a NEMS device and/or combinations thereof. ### Claim 15 (depends on 1) The package of claim 1, further comprising at least one thermal dielectric layer located between the at least one metal layer and the backside of the integrated device. ### Claim 16 (depends on 15) The package of claim 15, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 17 (depends on 15) The package of claim 15, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate, and wherein a majority of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate. ### Claim 18 (depends on 15) The package of claim 15, wherein the at least one thermal dielectric layer is located over the encapsulation layer, and wherein the at least one thermal dielectric layer is coupled to the backside of the integrated device and the at least one encapsulation layer interconnect. ### Claim 19 (depends on 1) The package of claim 1, wherein the at least one metal layer is located over a side surface of the encapsulation layer and a side surface of the substrate. ### Claim 20 (depends on 1) The package of claim 1, wherein the at least one encapsulation layer interconnects includes a plurality of encapsulation layer interconnects that laterally surround the integrated device. ### Claim 21 An apparatus comprising: a substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate; means for encapsulation located over the substrate; means for encapsulation layer interconnection located in the means for encapsulation, wherein the means for encapsulation layer interconnection is coupled to the substrate; and means for electromagnetic interference (EMI) shield located over the means for encapsulation, wherein the means for EMI shield is located over a backside of the integrated device. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the means for encapsulation layer interconnection includes at least one through mold via (TMV) and/or at least one wire bond. ### Claim 23 (depends on 21) The apparatus of claim 21, wherein the means for electromagnetic interference (EMI) shield includes at least one metal layer, and wherein the means for encapsulation layer interconnection includes at least one encapsulation layer interconnect. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the at least one metal layer and the at least one encapsulation layer interconnect is configured to be coupled to ground. ### Claim 25 (depends on 23) The apparatus of claim 23, wherein the at least one metal layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 26 (depends on 25) The apparatus of claim 25, wherein a majority of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, and (ii) the at least one metal layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 27 (depends on 23) The apparatus of claim 23, further comprising at least one thermal dielectric layer located between the at least one metal layer and the backside of the integrated device. ### Claim 28 (depends on 27) The apparatus of claim 27, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 29 (depends on 27) The apparatus of claim 27, wherein the at least one metal layer, the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate. ### Claim 30 (depends on 29) The apparatus of claim 29, wherein at least twenty percent (20%) of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one metal layer, (iv) the at least one encapsulation layer interconnect, and (v) the plurality of interconnects of the substrate. ### Claim 31 (depends on 23) The apparatus of claim 23, wherein the apparatus includes a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle. ### Claim 32 A package comprising: a substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate; an encapsulation layer located over the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; and at least one thermal dielectric layer located over the encapsulation layer, wherein the at least one thermal dielectric layer is located over a backside of the integrated device. ### Claim 33 (depends on 32) The package of claim 32, wherein the at least one thermal dielectric layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one thermal dielectric layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate. ### Claim 34 (depends on 32) The package of claim 32, wherein the at least one thermal dielectric layer includes a trench located over at least one encapsulation layer interconnect. ### Claim 35 (depends on 32) The package of claim 32, wherein the at least one encapsulation layer interconnect includes a though mold via (TMV), a wire bond, a metallized frame, and/or a surface mounted device (SMD). ### Claim 36 A method for fabricating a package, comprising: providing a substrate comprising: at least one dielectric layer; and a plurality of interconnects; coupling an integrated device to the substrate; forming an encapsulation layer located over the substrate; forming at least one encapsulation layer interconnect located in the encapsulation layer, wherein the encapsulation layer interconnect is coupled to the substrate; and forming at least one metal layer over the encapsulation layer, wherein the at least one metal layer is configured as an electromagnetic interference (EMI) shield for the package, and wherein the at least one metal layer is located over a backside of the integrated device. ### Claim 37 (depends on 36) The method of claim 36, wherein the at least one metal layer is configured as a conformal EMI shield for the package, and wherein the at least one encapsulation layer interconnect is configured as a compartmental EMI shield for the package. ### Claim 38 (depends on 36) The method of claim 36, wherein forming the at least one encapsulation layer interconnect includes forming a through mold via (TMV) in the encapsulation layer and/or forming at least one wire bond. ### Claim 39 (depends on 36) The method of claim 36, further comprising forming at least one thermal dielectric layer over the backside of the integrated device, wherein forming the at least one metal layer includes forming the at least one metal layer over the at least one thermal dielectric layer. ### Claim 40 (depends on 39) The method of claim 39, further comprising forming at least one thermal dielectric layer over the encapsulation layer, wherein the at least one thermal dielectric layer is coupled to the at least one encapsulation layer interconnect. ### Claim 41 A package comprising: a substrate comprising: at least one dielectric layer; and a plurality of interconnects; an integrated device coupled to the substrate; an encapsulation layer located over the substrate; at least one encapsulation layer interconnect located in the encapsulation layer, wherein the at least one encapsulation layer interconnect is coupled to the substrate; and at least one dielectricum layer located over the encapsulation layer, wherein the at least one dielectricum layer is located over a backside of the integrated device. ### Claim 42 (depends on 41) The package of claim 41, wherein the at least one dielectricum layer is configured as a thermal management layer for the package, and wherein the encapsulation layer interconnect is configured as a compartmental EMI shield for the package. ### Claim 43 (depends on 41) The package of claim 41, wherein the at least one encapsulation layer interconnect includes at least one through mold via (TMV) and/or at least one wire bond. ### Claim 44 (depends on 41) The package of claim 41, wherein the at least one dielectricum layer and the at least one encapsulation layer interconnect are configured to be coupled to ground. ### Claim 45 (depends on 41) The package of claim 41, wherein the at least one dielectricum layer and the at least one encapsulation layer interconnect are configured to dissipate heat from the integrated device through (i) the backside of the integrated device, (ii) the at least one dielectricum layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate, and wherein a majority of the heat that is generated by the integrated device is dissipated by heat conduction through (i) the backside of the integrated device, and (ii) the at least one dielectricum layer, (iii) the at least one encapsulation layer interconnect, and (iv) the plurality of interconnects of the substrate.