# US 2022/0285285 A1 · Memory device and method of manufacturing the same

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- Number: US 2022/0285285 A1
- Document ID: US20220285285A1
- Status: Published application
- Kind: A1
- Application number: 17/468,344
- Filed: 2021-09-07
- Published: 2022-09-08
- Earliest claimed: 2021-03-04
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yoo Hyun NOH
- Web page: https://patentgrep.com/patent/US20220285285A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 46/301: {for alignment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present technology relates to a memory device and a method of manufacturing the same. A memory device according to an embodiment of the present disclosure includes a main chip region, a chip guard region disposed adjacent to the main chip region, a plurality of chip guard patterns formed in the chip guard region, and a buffer slit formed in a space between the plurality of chip guard patterns.

## Claims

### Claim 1

A memory device comprising:
a main chip region;
a chip guard region disposed adjacent to the main chip region;
a plurality of chip guard patterns formed in the chip guard region; and
a buffer slit formed in a space between the plurality of chip guard patterns.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the plurality of chip guard patterns have a line shape parallel to each other.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein each of the plurality of chip guard patterns has a concavo-convex portion and extends in one direction.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein a concave portion of each of the plurality of chip guard patterns faces a convex portion of an adjacent chip guard,

### Claim 5 (depends on 1)

The memory device of claim 1, further comprising:
a first stack in which a plurality of plate electrodes and a plurality of interlayer insulating layers are alternately stacked on the main chip region; and
a plurality of cell plugs passing through the first stack in a vertical direction.

### Claim 6 (depends on 5)

The memory device of claim 5, further comprising:
a second stack in which a plurality of sacrificial layers and the plurality of interlayer insulating layers are alternately stacked in the chip guard region,
wherein the plurality of chip guard patterns pass through the plurality of sacrificial layers and the plurality of interlayer insulating layers in a vertical direction,

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the plurality of chip guard patterns that pass through the plate electrodes and the plurality of interlayer insulating layers are spaced apart from each other.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the buffer slit passes through the plurality of plate electrode layers and the plurality of interlayer insulating layers that are stacked in the space between the plurality of chip guard patterns.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the buffer slit is formed of a polysilicon layer.

### Claim 10

A method of manufacturing a memory device, the method comprising:
forming a stack in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked on a substrate in a main chip region, a scribe region, and a chip guard region between the main chip region and the scribe region;
forming a plurality of trenches that pass through the stack in the chip guard region;
forming sacrificial patterns in the plurality of trenches;
forming a slit that passes through the stack in a space between the plurality of trenches;
removing the sacrificial layers that are exposed through the slit and forming a plurality of plate electrodes in a space from which the sacrificial layers are removed;
removing the sacrificial patterns and forming chip guard patterns in a space from which the sacrificial patterns are removed; and
forming a buffer slit in the slit.

### Claim 11 (depends on 10)

The method of claim 10, wherein the sacrificial patterns are formed of an oxide layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
performing a heat treatment process after forming the slit, wherein the sacrificial patterns generate stress in a direction of the main chip region and the scribe region during the heat treatment process.

### Claim 13 (depends on 10)

The method of claim 10, wherein the chip guard patterns are formed of a metal layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein the buffer slit is formed of a polysilicon layer.

### Claim 15

A method of manufacturing a memory device, the method comprising:
forming a stack in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked on a substrate in a main chip region and a chip guard region;
forming a plurality of trenches that pass through the stack in the chip guard region;
forming sacrificial patterns in the plurality of trenches;
forming a plurality of first slits that pass through the stack on the main chip region and forming a second slit that passes through the stack in a space between the plurality of trenches;
removing the sacrificial layers that are exposed through the first slits and the second slits and then forming a plurality of plate electrodes in a space from which the sacrificial layers are removed;
forming a plurality of chip guard patterns by filling each of the plurality of trenches with a conductive material after removing the sacrificial patterns; and
forming a buffer slit in the second slit.

### Claim 16 (depends on 15)

The method of claim 15, wherein the sacrificial patterns are formed of an oxide layer.

### Claim 17 (depends on 15)

The method of claim 15, further comprising:
performing a heat treatment process after forming the first slits and the second slits,
wherein the sacrificial patterns generate stress in a direction of the main chip region during the heat treatment process.

### Claim 18 (depends on 15)

The method of claim 15, wherein the chip guard patterns are formed of a metal layer,

### Claim 19 (depends on 15)

The method of claim 15, wherein the buffer slit is formed of a polysilicon layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein the plurality of trenches are formed to have a smooth line shape that are parallel to each other in one direction or to have a line shape with concavo-convex portions, each extending in the one direction.