# US 2022/0285282 A1 · Substrate structures and semiconductor structures

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- Number: US 2022/0285282 A1
- Document ID: US20220285282A1
- Status: Published application
- Kind: A1
- Application number: 17/752,793
- Filed: 2022-05-24
- Published: 2022-09-08
- Earliest claimed: 2020-06-11
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Wu Chou HSU; Min-Yao CHEN
- Web page: https://patentgrep.com/patent/US20220285282A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 44/00: Electrical arrangements for controlling or matching impedance
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07236: {Soldering or alloying}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/30: Die-attach connectors
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.

## Claims

### Claim 1

A substrate structure, comprising:
a substrate;
a first electronic component disposed within the substrate; and
a second electronic component disposed within the substrate,
wherein a first vertical dimension of the first electronic component is different from a second vertical dimension of the second electronic component, and a horizontal central axis of the first electronic component is substantially aligned with a horizontal central axis of the second electronic component.

### Claim 2 (depends on 1)

The substrate structure of claim 1, further comprising:
a first portion located at a vertical projection direction of the first electronic component, and wherein the first portion of the substrate structure is symmetric with respect to the horizontal central axis of the first electronic component.

### Claim 3 (depends on 2)

The substrate structure of claim 2, further comprising:
a second portion comprising a plurality of patterned conductive layers and located at a vertical projection direction of the second electronic component and disposed symmetrically with respect to the horizontal central axis of the second electronic component.

### Claim 4 (depends on 1)

The substrate structure of claim 1, further comprising:
a patterned conductive layer comprising a first pad electrically connected to the first electronic component and a second pad electrically connected to the second electronic component,
wherein the first pad is substantially level with the second pad, and wherein a first vertical distance between the first pad and the first electronic component is different from a second vertical distance between the second pad and the second electronic component.

### Claim 5 (depends on 4)

The substrate structure of claim 4, further comprising at least one first patterned conductive layer over the first electronic component and at least one second patterned conductive layer over the second electronic component, wherein the number of the at least one first patterned conductive layer is more than the number of the at least one second patterned conductive layer.

### Claim 6 (depends on 1)

The substrate structure of claim 1, wherein the substrate comprises a core via located between the first electronic component and the second electronic component.

### Claim 7 (depends on 6)

The substrate structure of claim 6, wherein a vertical dimension of the core via is substantially equal to the first vertical dimension of the first electronic component.

### Claim 8 (depends on 1)

The substrate structure of claim 1, wherein the first electronic component comprises a capacitor, the second electronic component comprises an inductor, and a signal is transmitted from a lower surface of the substrate to an upper surface of the substrate through at least one of the first electronic component and the second electronic component.

### Claim 9

A semiconductor structure, comprising:
a substrate;
a first electronic component disposed within the substrate;
a second electronic component disposed within the substrate; and
a first build-up layer disposed over the first electronic component, wherein a top surface of the first build-up layer is substantially level with a top surface of the second electronic component.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a second build-up layer disposed under the first electronic component, wherein a bottom surface of the second build-up layer is substantially level with a bottom surface of the second electronic component.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, further comprising:
a trace layer disposed over the first electronic component and the second electronic component, wherein the trace layer is electrically connected to the first electronic component and the second electronic component.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the substrate comprises a first dielectric layer encapsulating the first electronic component and the second electronic component, and the trace layer is disposed on the first dielectric layer.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the substrate comprises a second dielectric layer encapsulating the first electronic component, wherein the first dielectric layer encapsulates the second dielectric layer.

### Claim 14 (depends on 9)

The semiconductor structure of claim 9, wherein the substrate comprises a core via located between the first electronic component and the second electronic component, wherein the first build-up layer is disposed above the core via and electrically connected to the core via and the first electronic component.

### Claim 15

A semiconductor structure, comprising:
a substrate;
a capacitor component disposed within the substrate; and
an inductor component disposed within the substrate, wherein the inductor component and the capacitor component are arranged horizontally,
wherein a top surface of the capacitor component is substantially level with a top surface of the inductor component.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, further comprising:
a first electronic device disposed over an upper surface of the substrate, wherein a signal is transmitted from a lower surface of the substrate to the first electronic device through at least one of the capacitor component and the inductor component.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, further comprising:
a second electronic device disposed under the lower surface of the substrate and electrically connected to the substrate.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein the capacitor component comprises a build-up layer configured to make a vertical dimension of the capacitor component substantially equal to a vertical dimension of the inductor component.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein the build-up layer comprises a via electrically connected to the capacitor component.

### Claim 20 (depends on 18)

The semiconductor structure of claim 18, wherein the build-up layer is disposed adjacent to the top surface or a bottom surface of the capacitor component.