# US 2022/0285271 A1 · Semiconductor memory device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285271 A1 - Document ID: US20220285271A1 - Status: Published application - Kind: A1 - Application number: 17/412,461 - Filed: 2021-08-26 - Published: 2022-09-08 - Earliest claimed: 2021-03-03 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Shota NIIHARA - Web page: https://patentgrep.com/patent/US20220285271A1 ## CPC - H10B 43/10: characterised by the top-view layout - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/42: Vias, e.g. via plugs - H10B 41/10: characterised by the top-view layout - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes a staircase portion, a columnar body, and a contact. The columnar body is provided in a second region of a stacked body, penetrating the stacked body in a stacking direction, and having a plurality of memory cells at each positions facing the plurality of conductive layers. The contact is connected to a terrace surface. Further, the staircases included in the staircase portion are each formed to ascend for each first step having conductive layers of the plurality of conductive layers in a second direction intersecting the stacking direction and a first direction. The terrace surfaces arranged in the first direction of the terrace surfaces of the staircases are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction. ## Claims ### Claim 1 A semiconductor memory device comprising: a staircase portion provided in a first region of a stacked body and provided with staircases, the stacked body having a plurality of conductive layers and a plurality of insulating layers stacked alternately one by one, the staircase portion having the conductive layers as terrace surfaces, and the staircases being arranged in n rows (where n is an integer of three or more) in a first direction intersecting a stacking direction of the stacked body; a columnar body provided in a second region of the stacked body, penetrating the stacked body in the stacking direction, and having a plurality of memory cells at each positions facing the plurality of conductive layers; and a contact connected to the terrace surface, wherein the staircases included in the staircase portion are each formed to ascend for each first step having p (n=p) conductive layers of the plurality of conductive layers in a second direction intersecting the stacking direction and the first direction, and the terrace surfaces arranged in the first direction of the terrace surfaces of the staircases are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a plate-like portion extending in the stacked body in the second direction and dividing the stacked body into a plurality of blocks including the first region and the second region. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein at least two of the staircase portions are provided in one of the blocks divided by the plate-like portion. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the terrace surface included in the staircase portion provided in one block includes a conductive layer of a layer different from that of the conductive layer constituting the terrace surface included in another staircase portion. ### Claim 5 (depends on 4) The semiconductor memory device according to claim 4, wherein one staircase portion of the staircase portions provided in one block includes the terrace surface including an uppermost conductive layer of the plurality of conductive layers, and another staircase portion of the staircase portions provided in one block includes the terrace surface including a lowest conductive layer of the plurality of conductive layers. ### Claim 6 (depends on 3) The semiconductor memory device according to claim 3, wherein the staircase portion provided in one block includes a first staircase portion and a second staircase portion adjacent to the first staircase portion, the staircases included in the first staircase portion are formed to ascend toward the second staircase portion for each first step, and the staircases included in the second staircase portion are formed to ascend toward the first staircase portion for each first step. ### Claim 7 (depends on 3) The semiconductor memory device according to claim 3, wherein the staircase portions provided in one block are arranged side by side in the second direction. ### Claim 8 (depends on 3) The semiconductor memory device according to claim 3, wherein the first region and the second region provided in one block are arranged side by side in the second direction. ### Claim 9 (depends on 2) The semiconductor memory device according to claim 2, wherein the staircase portions arranged in the first direction to sandwich the plate-like portion have a line-symmetric configuration to the plate-like portion in two adjacent blocks of the plurality of blocks. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the terrace surface arranged in the first direction of the terrace surfaces included individually in the staircase is formed to ascend for each second step toward the plate-like portion in each of the staircase portions provided in the two adjacent blocks. ### Claim 11 A method of manufacturing a semiconductor memory device, the method comprising: forming a stacked body by stacking a plurality of sacrificial layers and a plurality of insulating layers alternately one by one; forming a first mask having a planar-view rectangular shape on an upper surface of the stacked body; slimming the first mask and etching a surface of the stacked body exposed from the first mask one or more times; forming a second mask having four first openings on the stacked body after processing using the first mask, each of the first openings being in contact with portions in which four corners of the first mask are originally placed; slimming the second mask and etching a surface of the stacked body exposed from the second mask two or more times; forming a third mask having two second openings on the stacked body after processing using the second mask, one of the two second openings being across two portions in which the four first openings are originally placed and another of the two second openings being across other two portions in which the four first openings are originally placed; and slimming the third mask and etching a surface of the stacked body exposed from the third mask one or more times. ### Claim 12 (depends on 11) The method of manufacturing a semiconductor memory device according to claim 11, wherein the stacked body is etched with a first etching amount in one-time etching in a case of etching the surface of the stacked body exposed from the first mask and a case of etching the surface of the stacked body exposed from the second mask, the first etching amount corresponding to a thickness value of one of the plurality of sacrificial layers and one of the plurality of insulating layers. ### Claim 13 (depends on 12) The method of manufacturing a semiconductor memory device according to claim 12, wherein in a case of slimming the second mask and etching the surface of the stacked body exposed from the second mask j times (where j is an integer of two or more), when the surface of the stacked body exposed from the third mask is etched, the stacked body is etched with a second etching amount in one-time etching, the second etching amount corresponding to a thickness value of k (j=k) sacrificial layers of the plurality of sacrificial layers and k insulating layers of the plurality of insulating layers. ### Claim 14 (depends on 11) The method of manufacturing a semiconductor memory device according to claim 11, wherein the slimming of the first mask and the etching of the surface of the stacked body exposed from the first mask are performed one time, and the slimming of the second mask and the etching of the surface of the stacked body exposed from the second mask are performed two times. ### Claim 15 (depends on 14) The method of manufacturing a semiconductor memory device according to claim 14, wherein the slimming of the third mask and the etching of the surface of the stacked body exposed from the third mask are performed one time. ### Claim 16 (depends on 13) The method of manufacturing a semiconductor memory device according to claim 13, wherein in a case of slimming the first mask and etching the surface of the stacked body exposed from the first mask, the stacked body is etched with the first etching amount using the first mask to form a first convex portion, the first mask is slimmed, and the stacked body is etched with the first etching amount using the first mask subjected to the slimming to form a second convex portion and form a third convex portion on the second convex portion, the second convex portion being formed by transferring the first convex portion to a lower layer. ### Claim 17 (depends on 16) The method of manufacturing a semiconductor memory device according to claim 16, wherein in a case of slimming the second mask and etching the surface of the stacked body exposed from the second mask, the stacked body is etched with the first etching amount using the second mask to form four first concave portions in contact with respective four corners of the second convex portion, the second mask is slimmed to form four third openings to be larger than the first opening and be in contact with respective four corners of the third convex portion, the stacked body is etched to form four second concave portions and four third concave portions with the first etching amount using the second mask subjected to the slimming, the four second concave portions being in contact with the respective four corners of the third convex portion, and the four third concave portions being formed in the second concave portions by transferring the respective first concave portions to a lower layer, the second mask is further slimmed to form four fourth openings larger than the third opening, and the stacked body is etched with the first etching amount using the second mask being further subjected to the slimming to form four fourth concave portions, four fifth concave portions, and four sixth concave portions, the four fourth concave portions each having one corner entering inside each of the four corners of the third convex portion, the four fifth concave portions being formed in the fourth concave portion by transferring the respective second concave portions to a lower layer, and the four sixth concave portions being formed in the fifth concave portions by further transferring the respective third concave portions to a lower layer. ### Claim 18 (depends on 17) The method of manufacturing a semiconductor memory device according to claim 17, wherein in a case of slimming the third mask and etching the surface of the stacked body exposed from the third mask, the stacked body is etched with the second etching amount using the third mask to form two seventh concave portions by transferring respective regions including a part of the fifth concave portions and the sixth concave portions to a lower layer, the third mask is slimmed to form two fifth openings larger than the second opening, and the stacked body is etched with the second etching amount using the third mask subjected to the slimming to form two eighth concave portions and two ninth concave portions, the two eighth concave portions being formed by transferring a region including a part of the fourth concave portions and a part of the second convex portion to a lower layer, and the two ninth concave portions being formed in the eighth concave portions by further transferring the respective seventh concave portions to a lower layer. ### Claim 19 (depends on 11) The method of manufacturing a semiconductor memory device according to claim 11, further comprising: replacing the plurality of sacrificial layers with respective corresponding conductive layers after processing using the third mask. ### Claim 20 (depends on 19) The method of manufacturing a semiconductor memory device according to claim 19, wherein the plurality of sacrificial layers is formed of silicon nitride, and the conductive layer is formed of metal.