# US 2022/0285262 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0285262 A1 - Document ID: US20220285262A1 - Status: Published application - Kind: A1 - Application number: 17/750,481 - Filed: 2022-05-23 - Published: 2022-09-08 - Earliest claimed: 2014-12-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: JANG-GN YUN; JAESUN YUN; Joon-Sung LIM - Web page: https://patentgrep.com/patent/US20220285262A1 ## CPC - H10W 20/43: Layouts of interconnections - H10B 43/40: characterised by the peripheral circuit region - H10D 88/00: Three-dimensional [3D] integrated devices - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 74/147: {the encapsulations being multilayered} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate, The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; a first pattern on the semiconductor substrate; a second pattern disposed at substantially the same level as the first pattern and spaced apart from the second pattern; a peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern; a dummy interconnection structure on the semiconductor substrate; a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the first pattern; a cell vertical structure disposed on the first pattern and passing through the cell gate conductive patterns, wherein at least one side of the stacked structure has a staircase shape; and a dummy contact plug directly on and contacting the second pattern, wherein a portion of the cell vertical structure directly contacts the first pattern, wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell gate conductive patterns, wherein a lower end of the dummy contact plug is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns. wherein the dummy interconnection structure is electrically isolated, wherein the dummy interconnection structure includes dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate, wherein the d umm y patterns include: a first dummy pattern; and a second dummy pattern disposed at a higher level than the first dummy pattern, wherein the peripheral circuit includes: a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern; and a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern.. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first pattern and the second pattern include the same material. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first pattern includes a first layer and a second layer on the first layer, and wherein the second layer is different from the first layer. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein each of the first pane and the second pattern includes polysilicon. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first pattern and the second pattern have substantially the same thickness. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the dummy patterns further include a dummy gate pattern, wherein the peripheral circuit further includes a peripheral, gate disposed at substantially the same level as the dummy gate pattern, and wherein the dummy gate pattern is at a lower level than the first dummy pattern. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the dummy patterns further include a third dummy pattern disposed at a higher level than the second dummy pattern. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein at least a portion of the third dummy pattern overlaps at least one of at least a portion of the first dummy pattern or at least a portion of the second dummy pattern in the vertical direction. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein at least a portion of the second dummy pattern overlaps at least a portion of the first dummy pattern in the vertical direction. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the dummy contact plug is a single dummy contact plug electrically connected to the the second pattern. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the cell vertical structure includes a channel layer, a first dielectric layer, a second dielectric layer and a data storage layer, wherein the cell gate conductive patterns include word lines, wherein the data storage layer is between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer is between the channel layer and the data storage layer, and wherein the channel layer contacts the first pattern. ### Claim 12 A semiconductor device, comprising: a semiconductor substrate; a first pattern on the semiconductor substrate; a second pattern disposed at substantially the same level as the first pattern and spaced apart from the first pattern; peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern; a dummy interconnection structure on the semiconductor substrate; a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from web other in vertical direction perpendicular to an upper surface of the first pattern; a cell vertical structure disposed on the first pattern, passing through the cell gate conductive patterns, and directly contacting the first pattern; and a dummy contact plug directly contacting the second pattern, wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell Mate conductive patterns, wherein a lower end of the dummy contact plug is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns, wherein at least one side of the stacked structure has a staircase shape, wherein the dummy interconnection structure is electrically isolated, wherein the dummy interconnection structure includes at least three dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate, wherein the at least three dummy patterns include: a dummy gate pattern; a first dummy pattern disposed at a higher level than the dummy gate pattern; and a second dummy pattern disposed at a higher level than the first dummy pattern, and wherein the peripheral circuit includes: a peripheral gate disposed at substantially the same level as the dummy gate pattern; a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern; and a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first pattern and the second pattern include the same material and have substantially the same thickness. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the first pattern includes a first layer and a second layer on the first layer, and wherein the second layer is different from the first layer. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein each of the first pattern and the second pattern includes polysilicon. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein at least a portion of the second dummy pattern overlaps at least one of at least a portion of the dummy gate pattern or at least a portion of the first dummy pattern in the vertical direction. ### Claim 17 (depends on 12) The semiconductor device of claim 12, further comprising: a bit line; and a bit line dummy contact plug between the bit line and the cell vertical structure, wherein the cell vertical structure includes a channel layer, a first dielectric layer, a second dielectric layer and a data storage layer, wherein the cell gate conductive patterns include word lines, wherein the data storage layer is between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer is between the channel layer and the data storage layer, and wherein the channel layer contacts the first pattern. ### Claim 18 An electronic system, comprising: a memory device; and a processor to control the memory device, wherein the memory device comprises: a semiconductor substrate; a first pattern on the semiconductor substrate; a second pattern disposed at substantially the same level as the first pattern and spaced apart from the second pattern; a peripheral circuit on the semiconductor substrate, at least a portion of the peripheral circuit being between the semiconductor substrate and the first pattern; a dummy interconnection structure on the semiconductor substrate; a stacked structure including cell gate conductive patterns on the first pattern, the cell gate conductive patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the first pattern; a cell vertical structure disposed on the first pattern, passing through the cell gate conductive patterns, and directly contacting the first pattern; and a dummy contact plug directly contacting the second pattern, wherein an upper end of the dummy contact plug is at a higher level than an uppermost cell gate conductive pattern among the cell gate conductive patterns, wherein a lower end of the dummy contact plug, is at a lower level than a lowermost cell gate conductive pattern among the cell gate conductive patterns, wherein at least one side of the stacked structure has a staircase shape, wherein the dummy interconnection structure is electrically isolated, wherein the dummy interconnection structure includes at least three dummy patterns disposed at different levels from each other with respect to an upper surface of the semiconductor substrate, wherein the at least three dummy patterns include: a dummy gate pattern; a first dummy pattern disposed at a higher level than the dummy gate pattern; and a second dummy pattern disposed at a higher level than the first dummy pattern, and wherein the peripheral circuit includes: a peripheral gate disposed at substantially the same level as the dummy gate pattern; a first peripheral interconnection pattern disposed at substantially the same level as the first dummy pattern; and a second peripheral interconnection pattern disposed at substantially the same level as the second dummy pattern. ### Claim 19 (depends on 18) The electronic system of claim 18, wherein the cell vertical structure includes a channel layer, a first dielectric layer, a second dielectric layer and a data storage layer, wherein the cell gate conductive patterns include word lines, wherein the data storage layer is between the first dielectric layer and the second dielectric layer, wherein the second dialectric layer is between the channel layer and the data storage layer, and wherein the channel layer contacts the first pattern, ### Claim 20 (depends on 18) The electronic system of claim 18, wherein at least a portion of the second dummy pattern overlaps at least one of at least a portion of the dummy gate pattern or at least a portion of the first dummy pattern in the vertical direction.