# US 2022/0285261 A1 · Semiconductor structure and manufacturing method thereof

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- Number: US 2022/0285261 A1
- Document ID: US20220285261A1
- Status: Published application
- Kind: A1
- Application number: 17/465,744
- Filed: 2021-09-02
- Published: 2022-09-08
- Earliest claimed: 2021-03-08
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yexiao Yu; Zhongming Liu; Jia Fang
- Web page: https://patentgrep.com/patent/US20220285261A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/482: {Bit lines}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

## Claims

### Claim 1

A manufacturing method of a semiconductor structure, comprising:
providing a substrate, the substrate comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals and the polysilicon layer is electrically connected to an Active Area in the substrate;
forming a first insulating layer on the sacrificial layer, the first insulating layer covering a top surface of the sacrificial layer, a bottom of the first trench, and sidewalls of the first trench;
forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer;
removing the first insulating layer located at the bottom of the first trench;
removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and
removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a bit line structure.

### Claim 2 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, comprising:
depositing a carbon material on the surface of the first insulating layer above the top surface of the sacrificial layer to form the protective layer.

### Claim 3 (depends on 2)

The manufacturing method of a semiconductor structure according to claim 2, wherein the step of forming a protective layer comprises:
carrying out a plasma reaction to decompose CH4 into a carbon layer, the carbon layer being deposited on the surface of the first insulating layer above the top surface of the sacrificial layer.

### Claim 4 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, comprising:
forming the first insulating layer by an atomic layer deposition process.

### Claim 5 (depends on 4)

The manufacturing method of a semiconductor structure according to claim 4, wherein:
the first insulating layer being made of silicon dioxide.

### Claim 6 (depends on 5)

The manufacturing method of a semiconductor structure according to claim 5, comprising:
after the step of forming the protective layer, performing a step of removing the first insulating layer located at the bottom of the first trench in situ.

### Claim 7 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, wherein the step of removing the first insulating layer located at the bottom of the first trench comprises:
by using the protective layer as a mask, etching the first insulating layer located at the bottom of the first trench by an etching process.

### Claim 8 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, wherein the step of removing the protective layer, part of the first insulating layer, the sacrificial layer and part of the mask layer to form the first pattern layer comprises:
carrying out an etching process to remove the protective layer;
carrying out a planarization process to remove the first insulating layer above the top surface of the sacrificial layer; and
carrying out an etching process to remove the sacrificial layer and part of the mask layer.

### Claim 9 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, wherein the substrate further comprises: a metal barrier layer located between the polysilicon layer and the first conductive layer.

### Claim 10 (depends on 1)

The manufacturing method of a semiconductor structure according to claim 1, after the step of forming the bit line structure, the method further comprises:
forming a bit line isolation layer at least covering the sidewall of the bit line structure.

### Claim 11 (depends on 10)

The manufacturing method of a semiconductor structure according to claim 10, wherein the step of forming the bit line isolation layer comprises:
forming a first isolation layer at least covering the sidewall of the bit line structure.
forming a second isolation layer covering a surface of the first isolation layer; and
forming a third isolation layer covering a surface of the second isolation layer;
wherein the first isolation layer, the second isolation layer, and the third isolation layer constitute the bit line isolation layer.

### Claim 12 (depends on 11)

The manufacturing method of a semiconductor structure according to claim 11, wherein:
a material of the first isolation layer has a higher density than a material of the second isolation layer, the material of the first isolation layer has a higher dielectric constant than the material of the second isolation layer.

### Claim 13 (depends on 12)

The manufacturing method of a semiconductor structure according to claim 12, wherein:
the material of the first isolation layer is the same as the material of the third isolation layer.

### Claim 14 (depends on 13)

The manufacturing method of a semiconductor structure according to claim 13, wherein:
the material of the first isolation layer is silicon nitride and the material of the second isolation layer is silicon oxide.

### Claim 15 (depends on 1)

A semiconductor structure, comprising:
a substrate; and
a bit line structure located on a surface of the substrate, the bit line structure being formed by the manufacturing method of a semiconductor structure according to claim 1.