# US 2022/0285221 A1 · Graphene layer for low resistance contacts and damascene interconnects

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- Number: US 2022/0285221 A1
- Document ID: US20220285221A1
- Status: Published application
- Kind: A1
- Application number: 17/550,670
- Filed: 2021-12-14
- Published: 2022-09-08
- Earliest claimed: 2021-03-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Mrunal Abhijith Khaderbad; Wei-Yen Woon; Cheng-Ming Lin; Han-Yu Lin; Szu-Hua Chen; Jhih-Rong Huang; Tzer-Min Shen
- Web page: https://patentgrep.com/patent/US20220285221A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/033: {in openings in dielectrics}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/0111: {to Group IV semiconductors}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0158: {the components including FinFETs}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4437: {the principal metal being a transition metal}
- H10W 70/095: {of vias therein}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a fin structure, on the substrate, comprising an epitaxial region;
an etch stop layer on the epitaxial region;
an interlayer dielectric layer on the etch stop layer;
a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer; and
a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the fin structure is a merged fin structure; and
the epitaxial region is a merged epitaxial region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
an other fin structure, on the substrate, comprising an other epitaxial region;
a barrier layer on a top surface of the other epitaxial region;
an other metal contact above the barrier layer; and
a liner layer at an interface between the other metal contact and the barrier layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein:
the epitaxial region is an n-type epitaxial region; and
the other epitaxial region is a p-type epitaxial region.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein:
the epitaxial region is a p-type epitaxial region; and
the other epitaxial region is an n-type epitaxial region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
an other fin structure, on the substrate, comprising an other epitaxial region having an opposite type from that of the epitaxial region; and
an other graphene film at an interface between the other metal contact and the other interlayer dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the graphene film is between 0.3 nm and 5 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a via on a top surface of the metal contact; and
an other graphene film on a sidewall of the via.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a metal plug on a top surface of the via; and
a third graphene film on a sidewall of the metal plug.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
an other metal plug on a top surface of the metal plug; and
an other graphene film on a sidewall of the other metal plug.

### Claim 11

A method of forming a semiconductor device, comprising:
forming a fin structure with an epitaxial layer;
forming a catalyst layer in an opening that exposes a top surface of the epitaxial layer;
forming a graphene film at an interface between the catalyst layer and the epitaxial layer; and
forming a metal plug on the graphene film to fill the opening.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
prior to forming the metal plug, removing the catalyst layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
forming the catalyst layer comprises depositing a first metal; and
forming the metal plug comprises depositing a second metal different from the first metal.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
forming the catalyst layer comprises depositing a first metal; and
forming the metal plug comprises depositing the first metal on the catalyst layer, wherein the catalyst layer is used as a seeding layer.

### Claim 15 (depends on 11)

The method of claim 11, wherein:
forming the catalyst layer comprises depositing a first metal; and
forming the metal plug comprises depositing a second metal on the catalyst layer, wherein the catalyst layer is used as a seeding layer and the second metal is different from the first metal.

### Claim 16

A method of forming a semiconductor device, comprising:
forming a fin structure with an epitaxial layer;
forming a graphene seeding layer in an opening that exposes a top surface of the epitaxial layer;
forming a graphene film by heating the graphene seeding layer to drive precipitation and growth of carbon atoms in the graphene seeding layer; and
forming a metal plug on the graphene film to fill the opening.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the graphene seeding layer comprises using 1,2,3,4-tetraphenylnaphthalene, Pyrene, or Benzene as a carbon source.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the graphene film comprises heating the graphene seeding layer by one of an ultraviolet curing process, a laser treatment process, and a thermal anneal process.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the metal plug comprises:
depositing a metal in the opening; and
performing an activation annealing process at a temperature between about 380° C. and about 450° C. in argon or a vacuum.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
prior to forming the graphene seeding layer, forming an epitaxial termination interface by treating the top surface of the epitaxial layer.