# US 2022/0285151 A1 · Single crystal semiconductor structure and method of manufacturing the same

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- Number: US 2022/0285151 A1
- Document ID: US20220285151A1
- Status: Published application
- Kind: A1
- Application number: 17/352,851
- Filed: 2021-06-21
- Published: 2022-09-08
- Earliest claimed: 2021-03-08
- Assignees: Samsung Electronics Co., Ltd.; iBeam Materials, Inc.
- Applicants: Samsung Electronics Co., Ltd.; iBeam Materials, Inc.
- Inventors: Junhee CHOI; Vladmir MATIAS; Joohun HAN
- Web page: https://patentgrep.com/patent/US20220285151A1

## CPC

- H10P 14/3248: {consisting of two layers}
- H10D 62/405: {Orientations of crystalline planes}
- H10P 14/3238: {being insulating materials}
- H10P 14/3241: {being conductive materials}
- H10P 14/3244: {Layer structure}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3256: {Microstructure}
- H10P 14/3258: {Crystal orientation}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/3458: {Monocrystalline}
- H10P 14/20: of semiconductor materials
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2922: {being non-crystalline insulating materials, e.g. glass or polymers}
- H10P 14/2923: {being conductive materials, e.g. metallic silicides}
- H10P 14/3216: {Nitrides}
- H10P 14/3218: {Phosphides}
- H10P 14/3221: {Arsenides}
- H10P 14/3416: {Nitrides}
- H10P 14/3418: {Phosphides}
- H10P 14/3421: {Arsenides}
- H10P 14/3466: {Crystal orientation}
- H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A single crystal semiconductor includes a strain compensation layer; an amorphous substrate disposed on the strain compensation layer; a lattice matching layer disposed on the amorphous substrate and including two or more single crystal layers; and a single crystal semiconductor layer disposed on the lattice matching layer, the lattice matching layer including a direction control film disposed on the amorphous substrate and including a single crystal structure, and a buffer layer including a material different from that of the direction control film, the buffer layer being disposed on the direction control film and including a single crystal structure.

## Claims

### Claim 1

A single crystal semiconductor structure comprising:
a strain compensation layer;
an amorphous substrate disposed on the strain compensation layer;
a lattice matching layer disposed on the amorphous substrate, the lattice matching layer comprising two or more single crystal layers; and
a single crystal semiconductor layer disposed on the lattice matching layer,
wherein the lattice matching layer comprises a direction control film disposed on the amorphous substrate, the direction control film comprising a single crystal structure, and a buffer layer comprising a material different from a material of the direction control film, the buffer layer being disposed on the direction control film and comprising a single crystal structure,
wherein a thickness of the direction control film is equal to or less than 10 times a critical thickness hc, and
wherein the critical thickness hc is determined by a following equation:
h
c
=
[
b
4
⁢
π
⁡
(
1
+
μ
)
⁢
ϵ
0
)
]
[
ln
⁡
(
h
c
b
)
+
1
]
(b: Burgers vector, μ: Poisson's ratio, and ε0: a degree of lattice misfit between the direction control film and the single crystal semiconductor layer).

### Claim 2 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein, a first difference between a coefficient of thermal expansion of the strain compensation layer and a coefficient of thermal expansion of the single crystal semiconductor layer is less than a second difference between a coefficient of thermal expansion of the amorphous substrate and the coefficient of thermal expansion of the single crystal semiconductor layer.

### Claim 3 (depends on 2)

The single crystal semiconductor structure of claim 2, wherein the first difference is equal to or less than 10% of the coefficient of thermal expansion of the single crystal semiconductor layer within a temperature range of about 200° C. to about 1200° C.

### Claim 4 (depends on 3)

The single crystal semiconductor structure of claim 3, wherein the strain compensation layer comprises a molybdenum (Mo) alloy.

### Claim 5 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein a lattice structure of the direction control film matches a lattice structure of the buffer layer.

### Claim 6 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein a crystal of the direction control film is oriented in a (111) direction.

### Claim 7 (depends on 6)

The single crystal semiconductor structure of claim 6, wherein the direction control film comprises CeO2 or Sc2O3.

### Claim 8 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein the buffer layer comprises a single layer comprising MgO or AlN.

### Claim 9 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises CeO2 or Sc2O3 formed by a deposition process different from a deposition process of the direction control film, and
wherein the second buffer layer comprises MgO or AlN.

### Claim 10 (depends on 1)

The single crystal semiconductor structure of claim 1, wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises MgO or AlN, and
wherein the second buffer layer comprises a same material as a material of the single crystal semiconductor layer.

### Claim 11 (depends on 10)

The single crystal semiconductor structure of claim 10, wherein a crystallinity of the single crystal semiconductor layer is higher than a crystallinity of the second buffer layer.

### Claim 12 (depends on 1)

The single crystal semiconductor structure of claim 1, further comprising:
a mask pattern disposed between the single crystal semiconductor layer and the lattice matching layer,
wherein the mask pattern comprises holes exposing the lattice matching layer, and
wherein the single crystal semiconductor layer is disposed on the mask pattern and fills the holes.

### Claim 13 (depends on 1)

The single crystal semiconductor structure of claim 1, further comprising a heat dispersion layer disposed between the lattice matching layer and the amorphous substrate.

### Claim 14 (depends on 13)

The single crystal semiconductor structure of claim 13, further comprising a planarization layer disposed between the heat dispersion layer and the lattice matching layer,
wherein a surface roughness of an upper surface of the planarization layer facing the lattice matching layer is less than a surface roughness of a lower surface of the planarization layer facing the heat dispersion layer.

### Claim 15

A method of manufacturing a single crystal semiconductor structure, the method comprising:
providing an amorphous substrate;
forming a strain compensation layer on a lower surface of the amorphous substrate;
forming a lattice matching layer on the amorphous substrate, the lattice matching layer comprising two or more single crystal layers; and
forming a single crystal semiconductor layer on the lattice matching layer,
wherein the lattice matching layer comprises a direction control film disposed on the amorphous substrate, the direction control film comprising a single crystal structure, and a buffer layer comprising a material different from the direction control film, the buffer layer being disposed on the direction control film and comprising a single crystal structure,
wherein a thickness of the direction control film is less than 10 times a critical thickness hc, and
wherein the critical thickness hc is determined by a following equation:
h
c
=
[
b
4
⁢
π
⁡
(
1
+
μ
)
⁢
ϵ
0
)
]
[
ln
⁡
(
h
c
b
)
+
1
]
(b: Burgers vector, μ: Poisson's ratio, and ε0: a degree of lattice misfit between the direction control film and the single crystal semiconductor layer).

### Claim 16 (depends on 15)

The method of claim 15, wherein, a first difference between a coefficient of thermal expansion of the strain compensation layer and a coefficient of thermal expansion of the single crystal semiconductor layer is less than a second difference between a coefficient of thermal expansion of the amorphous substrate and the coefficient of thermal expansion of the single crystal semiconductor layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first difference is equal to or less than 10% of the coefficient of thermal expansion of the single crystal semiconductor layer within a temperature range of about 200° C. to about 1200° C.

### Claim 18 (depends on 17)

The method of claim 17, wherein the strain compensation layer comprises a molybdenum (Mo) alloy.

### Claim 19 (depends on 15)

The method of claim 15, wherein the strain compensation layer and the single crystal semiconductor layer are formed in a first temperature range, and
wherein the lattice matching layer is formed in a second temperature range that lower than the first temperature range.

### Claim 20 (depends on 15)

The method of claim 15, wherein the direction control film is formed by an ion beam assisted deposition (IBAD) process.

### Claim 21 (depends on 20)

The method of claim 20, wherein a crystal of the direction control film is oriented in a (111) direction.

### Claim 22 (depends on 21)

The method of claim 21, wherein the direction control film comprises CeO2 or Sc2O3.

### Claim 23 (depends on 20)

The method of claim 20, wherein the buffer layer comprises a single layer comprising MgO or AlN.

### Claim 24 (depends on 20)

The method of claim 20, wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises CeO2 or Sc2O3 formed by a deposition process different from a deposition process of the direction control film, and
wherein the second buffer layer comprises MgO or AlN.

### Claim 25 (depends on 15)

The method of claim 15, wherein the buffer layer comprises a first buffer layer disposed on the direction control film and a second buffer layer disposed on the first buffer layer, the second buffer layer comprising a material different from the first buffer layer,
wherein the first buffer layer comprises MgO or AlN, and
wherein the second buffer layer comprises a same material as a material of the single crystal semiconductor layer.

### Claim 26 (depends on 25)

The method of claim 25, wherein a crystallinity of the single crystal semiconductor layer is higher than a crystallinity of the second buffer layer.

### Claim 27 (depends on 15)

The method of claim 15, further comprising forming a mask pattern on the lattice matching layer before forming the single crystal semiconductor layer,
wherein the mask pattern comprises holes exposing the lattice matching layer, and
wherein the single crystal semiconductor layer is disposed on the mask pattern and fills the holes.

### Claim 28 (depends on 15)

The method of claim 15, further comprising forming a heat dispersion layer on the amorphous substrate before forming the lattice matching layer.

### Claim 29 (depends on 28)

The method of claim 28, further comprising forming a planarization layer on the heat dispersion layer before forming the lattice matching layer,
wherein a surface roughness of an upper surface of the planarization layer facing the lattice matching layer is less than a surface roughness of a lower surface of the planarization layer facing the heat dispersion layer.