Signed multiword multiplier
AssigneeGoogle Inc.
InventorReiner Pope
Life of this patent
Estimating the term…
Abstract
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a hardware circuit configured as a signed multiword multiplier. The circuit includes a processing circuit that receives inputs that each have a respective bit-width. The processing circuit can represent at least one input as a signed multiword input based on the first input having a bit-width that exceeds a fixed bit-width of the hardware circuit. The circuit includes signed multipliers that are each configured to multiply signed inputs. Each signed multiplier includes multiplication circuitry configured to: receive the signed multiword input; receive a signed second input; and generate a signed output in response to multiplying the signed multiword input with the signed second input.
Claims20
A hardware circuit for multiplying sets of inputs, the hardware circuit comprising:
- processing circuitry that receives a first input and a second input, each of the first and second inputs having a respective bit-width, wherein the processing circuitry is configured to represent at least the first input as a signed multiword input based on the first input having a bit-width that exceeds a fixed bit-width of the hardware circuit;
- and
- one or more signed multipliers, each of the one or more signed multipliers being configured to multiply two or more signed inputs, each signed multiplier comprising multiplication circuitry configured to:
- receive the signed multiword input that represents the first input;
- receive a signed second input that corresponds to the second input;
- and
- generate a signed output in response to multiplying the signed multiword input with the signed second input.
A method for multiplying sets of inputs using a hardware circuit, the method comprising:
- receiving, by a processing circuit of the hardware circuit, a first input and a second input, each of the first and second inputs having a respective bit-width, wherein at least the first input has a bit-width that exceeds a fixed bit-width of multiplication hardware included in the hardware circuit, the multiplication hardware being used to multiply the first and second inputs;
- generating, from at least the first input, a signed multiword input comprising a plurality of signed words that each have a plurality of bits, wherein a bit-width of the signed multiword input is less than the fixed bit-width of the multiplication hardware;
- providing the signed multiword input and a signed second input to the multiplication hardware for multiplication, wherein the signed second input corresponds to the second input and has a bit-width that is within the fixed bit-width of the multiplication hardware;
- and
- generating a signed output from the multiplication hardware using at least the first and second inputs.
One or more non-transitory machine-readable storage devices of a hardware circuit and for storing instructions that are executable by one or more processing devices to cause performance of operations comprising:
- receiving, by a processing circuit of the hardware circuit, a first input and a second input, each of the first and second inputs having a respective bit-width, wherein at least the first input has a bit-width that exceeds a fixed bit-width of multiplication hardware included in the hardware circuit, the multiplication hardware being configured to multiply the first and second inputs;
- generating, from at least the first input, a signed multiword input comprising a plurality of signed words that each have a plurality of bits, wherein a bit-width of the signed multiword input is less than the fixed bit-width of the multiplication hardware;
- providing the signed multiword input and a signed second input to the multiplication hardware for multiplication, wherein the signed second input corresponds to the second input and has a bit-width that is less than the fixed bit-width of the multiplication hardware;
- and
- generating a signed output from the multiplication hardware using at least the first and second inputs.
Dependencies are inferred from the claim text.