# US 2022/0279079 A1 · Signal processing device, imaging device, reading device, image forming device, and signal processing method

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- Number: US 2022/0279079 A1
- Document ID: US20220279079A1
- Status: Published application
- Kind: A1
- Application number: 17/749,146
- Filed: 2022-05-20
- Published: 2022-09-01
- Earliest claimed: 2019-11-25
- Assignees: Ricoh Company, Ltd.
- Inventors: Shinji SAKAGUCHI; Tohru KANNO; Masamoto NAKAZAWA
- Web page: https://patentgrep.com/patent/US20220279079A1

## CPC

- G06F 13/4018: {with data-width conversion}
- H04N 1/00236: {using an image reading or reproducing device, e.g. a facsimile reader or printer, as a local input to or local output from a computer (image input to or image output from a computer via a network H04N1/00209)}
- H04N 1/32368: {Functions of a still picture terminal memory associated with transmission}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A signal processing device includes a data writing unit, a channel number converting unit, and a plurality of serial data transferring unit. The data writing unit is configured to write data of m channels into a memory. The channel number converting unit is configured to output the data read from the memory as data of n channels, where m is larger than n. The plurality of serial data transferring unit is configured to transfer the data of the n channels to a processing device in a subsequent stage.

## Claims

### Claim 1

A signal processing device comprising:
a data writing unit configured to write data of m channels into a memory;
a channel number converting unit configured to output the data read from the memory as data of n channels, m being larger than n; and
a plurality of serial data transferring unit configured to transfer the data of the n channels to a processing device in a subsequent stage.

### Claim 2 (depends on 1)

The signal processing device according to claim 1, further comprising a speed converting unit configured to cause data reading speed from the memory to be larger as compared to data writing speed into the memory, wherein
the channel number converting unit is configured to convert the data of the m channels into the data of n channels, the data reading speed of the data of the m channels being made larger by the speed converting unit.

### Claim 3 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit includes a circuit configured to generate a clock for writing the data into the memory, and a circuit configured to generate a clock for reading the data from the memory.

### Claim 4 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit is configured to cause a frequency of reading the data from the memory to be m/n times a frequency of writing the data into the memory.

### Claim 5 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit is configured to cause a frequency of reading the data from the memory to be equal to or more than m/n times a frequency of writing the data into the memory.

### Claim 6 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit is configured to cause a frequency of reading the data from the memory to be equal to or less than m/n times a frequency of writing the data into the memory.

### Claim 7 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit is configured to, even when converting data of different numbers of channels m1 and m2 as the data of the m channels into the data of the n channels, control frequencies of reading the data from the memory to be the same.

### Claim 8 (depends on 1)

The signal processing device according to claim 1, wherein the data writing unit is configured to write only the data of the n channels among the data of the m channels into the memory when only the data of the n channels are required.

### Claim 9 (depends on 2)

The signal processing device according to claim 2, wherein the speed converting unit is configured to read only the data of the n channels selected in advance from the data of the m channels written into the memory when only the data of the n channels is required.

### Claim 10 (depends on 2)

The signal processing device according to claim 2, wherein the channel number converting unit is configured to cause the data of the n channels transferred per reference clock to be n data obtained from one desired channel among the data of m channels.

### Claim 11 (depends on 2)

The signal processing device according to claim 2, wherein the channel number converting unit is configured to select the data of the n channels transferred per reference clock, one by one from each of the m channels in order.

### Claim 12 (depends on 1)

An imaging device comprising a solid-state imaging element including:
a pixel array; and
the signal processing device according to claim 1, data read by the pixel array being input to the signal processing device.

### Claim 13 (depends on 12)

A reading device comprising:
a light source configured to emit light; and
the imaging device according to claim 12, the imaging device being configured to receive reflection light of the light emitted from the light source.

### Claim 14 (depends on 13)

An image forming device comprising:
the reading device according to claim 13; and
an image forming unit.

### Claim 15

A signal processing method performed in a signal processing device, the signal processing method comprising:
writing data of m channels into a memory; and
transferring the data of the m channels read from the memory to a processing device in a subsequent stage as a plurality of serial signals of n channels, m being larger than n.