# US 2022/0278134 A2 · Array substrate and method of manufacturing the same, and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0278134 A2 - Document ID: US20220278134A2 - Status: Published application - Kind: A2 - Application number: 17/298,493 - Filed: 2020-09-25 - Published: 2022-09-01 - Earliest claimed: 2019-09-25 - Assignees: Fuzhou Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Fuzhou BOE Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Bin LIN; Yong ZENG; Yazhou HUO; Liangliang LI; Zhouyu CHEN - Web page: https://patentgrep.com/patent/US20220278134A2 ## CPC - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 89/911: {using passive elements as protective elements} - H10K 59/1201: {Manufacture or treatment} - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10K 59/1315: {comprising structures specially adapted for lowering the resistance} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A method of manufacturing an array substrate includes: providing a base; forming a plurality of conductive lines on the base; forming an oxide semiconductor film on a side of the plurality of conductive lines away from the base, the oxide semiconductor film covering the plurality of conductive lines and being in direct contact with at least one conductive line, and the at least one conductive line being configured to discharge static electricity generated in the oxide semiconductor film; and patterning the oxide semiconductor film by using a photoetching process to remove a portion of the oxide semiconductor film that is in direct contact with the at least one conductive line, and form an oxide semiconductor layer including active layers of a plurality of oxide thin film transistors, the oxide semiconductor layer and the at least one conductive line being insulated from each other. ## Claims ### Claim 1 A method of manufacturing an array substrate, comprising: providing a base; forming a plurality of conductive lines on the base; forming an oxide semiconductor film on a side of the plurality of conductive lines away from the base, the oxide semiconductor film covering the plurality of conductive lines and being in direct contact with at least one conductive line, and the at least one conductive line being configured to discharge static electricity generated in the oxide semiconductor film; and patterning the oxide semiconductor film by using a photoetching process to remove a portion of the oxide semiconductor film that is in direct contact with the at least one conductive line, and form an oxide semiconductor layer including active layers of a plurality of oxide thin film transistors, the oxide semiconductor layer and the at least one conductive line being insulated from each other. ### Claim 2 (depends on 1) The method of manufacturing the array substrate according to claim 1, further comprising: before forming the oxide semiconductor film, forming a gate conductive layer including gates of the plurality of oxide thin film transistors, the gate conductive layer and the plurality of conductive lines being located on the same side of the base; forming a gate insulating film on a side of both the plurality of conductive lines and the gate conductive layer away from the base, the gate insulating film covering the plurality of conductive lines and the gate conductive layer; and patterning the gate insulating film to form a gate insulating layer with at least one via hole, an orthogonal projection of the at least one via hole on the base being at least partially overlapped with an orthogonal projection of the at least one conductive line on the base; wherein the oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole. ### Claim 3 (depends on 2) The method of manufacturing the array substrate according to claim 2, wherein a portion of a boundary of the orthogonal projection of the at least one conductive line on the base coincides with a portion of a boundary of the orthogonal projection of the at least one via hole on the base. ### Claim 4 (depends on 2) The method of manufacturing the array substrate according to claim 2, wherein a material of the plurality of conductive lines includes a metal material; and the plurality of conductive lines and the gate conductive layer are formed in a same patterning process. ### Claim 5 (depends on 1) The method of manufacturing the array substrate according to claim 1, further comprising: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the base, the source-drain conductive layer including sources and drains of the plurality of oxide thin film transistors that are in direct contact with respective active layers. ### Claim 6 (depends on 5) The method of manufacturing the array substrate according to claim 5, wherein the array substrate has a display area and a bezel area located beside the display area; the source-drain conductive layer further includes at least one auxiliary lead that is in direct contact with the at least one conductive line; the at least one conductive line and the at least one auxiliary lead are located in the bezel area; the at least one conductive line is configured to transmit a common voltage signal to the display area, or to perform an electrostatic protection on the array substrate; and the at least one auxiliary lead is configured to be connected in parallel with the at least one conductive line, so as to reduce a resistance of the at least one conductive line. ### Claim 7 (depends on 1) The method of manufacturing the array substrate according to claim 1, wherein a material of the oxide semiconductor film includes one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide. ### Claim 8 (depends on 1) The method of manufacturing the array substrate according to claim 1, wherein an orthogonal projection of the oxide semiconductor layer on the base is at most partially overlapped with an orthogonal projection of the at least one conductive line on the base. ### Claim 9 An array substrate, comprising: a base; a plurality of conductive lines disposed on a side of the base; and a plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of conductive lines being disposed on the same side of the base; wherein each oxide thin film transistor includes a gate, an active layer, a source, and a drain; active layers of the plurality of oxide thin film transistors are obtained by patterning an oxide semiconductor film that is in direct contact with at least one of the plurality of conductive lines, and the active layers and the at least one conductive line are insulated from each other. ### Claim 10 (depends on 9) The array substrate according to claim 9, further comprising a gate insulating layer disposed between gates and active layers of the plurality of oxide thin film transistors; wherein the gate insulating layer has at least one via hole, and an orthogonal projection of the at least one via hole on the base is at least partially overlapped with an orthogonal projection of the at least one conductive line on the base; and the oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole. ### Claim 11 (depends on 10) The array substrate according to claim 10, further comprising at least one auxiliary lead disposed on a side of the gate insulating layer away from the base; wherein the at least one auxiliary lead is in direct contact with the at least one conductive line through the at least one via hole. ### Claim 12 (depends on 9) The array substrate according to claim 9, further comprising at least one auxiliary lead made of a same material and arranged in a same layer as the source and the drain; wherein the at least one auxiliary lead is in direct contact with the at least one conductive line. ### Claim 13 (depends on 11) The array substrate according to claim 11, wherein an orthogonal projection of the at least one auxiliary lead on the base is at least partially overlapped with the orthogonal projection of the at least one conductive line on the base. ### Claim 14 (depends on 11) The array substrate according to claim 11, wherein a routing direction of the at least one auxiliary lead is same as a routing direction of the at least one conductive line. ### Claim 15 (depends on 10) The array substrate according to claim 10, further comprising a passivation layer disposed on a side of both sources and drains of the plurality of oxide thin film transistors away from the base; wherein a portion of the passivation layer is located in the at least one via hole, and is in direct contact with the at least one conductive line. ### Claim 16 (depends on 9) The array substrate according to claim 9, wherein the array substrate has a display area and a bezel area located beside the display area; the at least one conductive line is located in the bezel area; the at least one conductive line includes a common electrode line or an electrostatic protection line; the common electrode line is configured to transmit a common voltage signal to the display area; and the electrostatic protection line is configured to perform an electrostatic protection on the array substrate. ### Claim 17 (depends on 9) The array substrate according to claim 9, wherein the gate and the plurality of conductive lines are made of a same material and arranged in a same layer. ### Claim 18 (depends on 9) A display apparatus, comprising the array substrate according to claim 9. ### Claim 19 (depends on 18) The display apparatus according to claim 18, further comprising: an opposite substrate arranged opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the opposite substrate. ### Claim 20 (depends on 18) The display apparatus according to claim 18, further comprising a plurality of light-emitting devices disposed on a side of the plurality of oxide thin film transistors in the array substrate away from the base in the array substrate.