# US 2022/0277992 A1 · Semiconductor structure

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- Number: US 2022/0277992 A1
- Document ID: US20220277992A1
- Status: Published application
- Kind: A1
- Application number: 17/744,434
- Filed: 2022-05-13
- Published: 2022-09-01
- Earliest claimed: 2019-08-09
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Hao ZHANG; Xuezhen JING; Jingjing TAN; Tiantian ZHANG; Zhangru XIAO; Zengsheng XU
- Web page: https://patentgrep.com/patent/US20220277992A1

## CPC

- H10D 64/0112: {using conductive layers comprising silicides}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/0526: {by thermal treatment thereof}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a dielectric layer formed on the substrate;
an opening, formed through the dielectric layer;
a contact layer formed at bottom of the opening;
a blocking layer formed on a sidewall surface of the opening; and
a plug formed in the opening, wherein the plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the plug is made of a material including at least one of Co, Cu, W, Al, Ti, and Ta.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the blocking layer is made of a material including at least one of titanium nitride (TiNx) and tantalum nitride (TaNx).

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the contact layer is made of a material including at least one of ABCx, ACx, and BCx, wherein A is a metal, including Co, W, or Cu; B is a metal, including Ti, Ni, or W; C is a semiconductor material, including Si, Ge, or Se; and x is a natural number greater than 1.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the contact layer has a first portion and a second portion, and
the blocking layer is formed on the first portion and the plug is formed on the second portion.

### Claim 6 (depends on 5)

The semiconductor structure according to claim 5, wherein:
the first portion has a top surface higher than a top surface of the second portion.

### Claim 7 (depends on 5)

The semiconductor structure according to claim 5, further including:
a material layer formed on the second portion of the contact layer between the blocking layer and the plug.

### Claim 8 (depends on 7)

The semiconductor structure according to claim 7, further including:
the material layer has a top surface coplanar with a top surface of the blocking layer and a top surface of the plug.

### Claim 9 (depends on 7)

The semiconductor structure according to claim 7, further including:
the material layer has a bottom surface coplanar with a bottom surface of the blocking layer and lower than a bottom surface of the plug.