# US 2022/0276802 A1 · Nonvolatile memory device, memory controller, and reading method of storage device including the same

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- Number: US 2022/0276802 A1
- Document ID: US20220276802A1
- Status: Published application
- Kind: A1
- Application number: 17/522,578
- Filed: 2021-11-09
- Published: 2022-09-01
- Earliest claimed: 2021-02-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Youngdeok SEO; Jinyoung KIM; Sehwan PARK; Ilhan PARK
- Web page: https://patentgrep.com/patent/US20220276802A1

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a memory block including a first memory area connected to a first word line; and
control logic comprising:
an on-chip valley search (OVS) circuit configured to perform an OVS sensing operation on the memory block; and
a first buffer memory configured to store at least one variation table including variation information of a threshold voltage of memory cells connected to the first word line, obtained from the OVS sensing operation,
wherein the control logic is configured to:
perform a first reading operation on the first memory area in response to a first read command applied by a memory controller, the first reading operation including a first OVS sensing operation performed at a first OVS sensing level and a first main sensing operation performed at a first main sensing level reflecting the variation information in response to the first read command.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control logic is further configured to determine a weight reflecting the variation information included in the at least one variation table according to a detection case according to the first OVS sensing operation.

### Claim 3 (depends on 2)

The nonvolatile memory device of claim 2, wherein a first weight reflecting the variation information provided when the detection case is an edge case is higher than a second weight reflecting the variation information provided when the detection case is not the edge case.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control logic further comprises a selection logic configured to select at least one of the at least one variation table, based on a result of the first OVS sensing operation.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein the selection logic is further configured to select one of the at least one variation table according to a detection case according to the first OVS sensing operation, and
the first main sensing level at which the first main sensing operation is performed is a reading level in which the variation information included in the at least one variation table selected is reflected.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein the control logic is further configured to selectively update the at least one variation table based on a result of the first OVS sensing operation.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, wherein the memory block further includes a second memory area connected to a second word line, and
the control logic is further configured to, after the first reading operation on the first memory area is completed, input to the second memory area a second read command determined based on a history reading level table stored in the memory controller.

### Claim 8 (depends on 7)

The nonvolatile memory device of claim 7, wherein the at least one variation table further includes variation information of threshold voltages of memory cells connected to the second word line, and
the control logic is further configured to perform a second reading operation at a reading level in which the variation information is reflected.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first OVS sensing level at which the first OVS sensing operation is to be performed has a value different from the first main sensing level.

### Claim 10 (depends on 9)

The nonvolatile memory device of claim 9, wherein the first OVS sensing level is a default reading level.

### Claim 11

A memory controller comprising:
a processor;
control pins configured to provide control signals to at least one nonvolatile memory device including a first memory area connected to a first word line;
an error correction circuit configured to correct data read from the at least one nonvolatile memory device based on the control signals; and
a buffer memory configured to store a plurality of tables for compensating for a reading level of a reading operation of the at least one nonvolatile memory device,
wherein the processor is configured to input a first read command for performing a first reading operation on the first memory area using at least one variation table stored in the at least one nonvolatile memory device.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein the plurality of tables includes a history reading level table, and
the processor is further configured to update the history reading level table when error correction of data read by the first reading operation is successful.

### Claim 13 (depends on 12)

The memory controller of claim 12, wherein the at least one nonvolatile memory device further includes a second memory area connected to a second word line; and
the processor is further configured to input a second read command for performing a second reading operation on the second memory area to the at least one nonvolatile memory device, based on the history reading level table.

### Claim 14 (depends on 13)

The memory controller of claim 13, wherein the processor is further configured to input a variation flag together with the second read command to the at least one nonvolatile memory device, and
wherein the variation flag includes a signal allowing the at least one nonvolatile memory device to perform the second reading operation by reflecting variation information of threshold voltages of memory cells connected to the second word line.

### Claim 15 (depends on 12)

The memory controller of claim 12, further comprising a command selector configured to select a read command based on the history reading level table, the read command to be input to a nonvolatile memory device,
wherein the read command is configured to adjust information of the at least one variation table used in the first reading operation of the nonvolatile memory device.

### Claim 16

A reading method of a storage device, the reading method comprising:
performing, in at least one nonvolatile memory device, a first on-chip valley search (OVS) sensing operation on selected memory cells in response to a first read command received from a memory controller;
extracting variation information of threshold voltages of the selected memory cells and deterioration information of a memory block including the selected memory cells;
performing a first main sensing operation at a modified reading level based on the variation information and the deterioration information; and
outputting a result of the first OVS sensing operation and data of the first main sensing operation to the memory controller,
wherein the first OVS sensing operation and the first main sensing operation are defined as a first reading operation.

### Claim 17 (depends on 16)

The reading method of the storage device of claim 16, wherein the variation information is included in at least one variation table stored in the at least one nonvolatile memory device.

### Claim 18 (depends on 16)

The reading method of the storage device of claim 16, further comprising performing a second reading operation on other selected memory cells by receiving a second read command after terminating the first reading operation, and outputting second read data.

### Claim 19 (depends on 18)

The reading method of the storage device of claim 18, wherein the second read command is output together with a variation flag, and
wherein the variation flag includes a signal for performing the second reading operation using variation information of threshold voltages of the other selected memory cells included in the at least one nonvolatile memory device.

### Claim 20 (depends on 16)

The reading method of the storage device of claim 16, further comprising updating a history reading level table based on the deterioration information, after the first reading operation is terminated.