# US 2022/0276286 A1 · Voltage hold circuit, voltage monitoring circuit, and semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0276286 A1 - Document ID: US20220276286A1 - Status: Published application - Kind: A1 - Application number: 17/746,467 - Filed: 2022-05-17 - Published: 2022-09-01 - Earliest claimed: 2019-11-29 - Assignees: Socionext Inc. - Applicants: Socionext Inc. - Inventors: Kengo KOMIYA; Akimitsu TAJIMA; Takeshi KIMURA - Web page: https://patentgrep.com/patent/US20220276286A1 ## CPC - G01R 19/04: Measuring peak values {or amplitude or envelope} of AC or of pulses - G01R 19/2503: {for measuring voltage only, e.g. digital volt meters (DVM's) (G01R19/2506 - G01R19/257 take precedence)} - G05F 1/468: {characterised by reference voltage circuitry, e.g. soft start, remote shutdown} - G01R 19/16552: {in I.C. power supplies} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract The voltage hold circuit is a voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit including: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle. ## Claims ### Claim 1 A voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit comprising: a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal in the reset period every the processing cycle. ### Claim 2 (depends on 1) The voltage hold circuit according to claim 1, wherein the first hold circuit includes a first switch configured to connect a capacitor to a reference potential node having a lower potential than a power supply voltage node in the case where a voltage value of the input voltage signal is smaller than a voltage value held in the capacitor, and the second hold circuit includes a second switch configured to connect the capacitor to the power supply voltage node in the case where a voltage value of the input voltage signal is larger than a voltage value held in the capacitor. ### Claim 3 (depends on 2) The voltage hold circuit according to claim 2, wherein a reset signal indicating the hold period or the reset period is input, the first switch is brought into a state of being able to be turned on when the reset signal indicates the hold period, and the first switch is turned off when the reset signal indicates the reset period, and the second switch is brought into a state of being able to be turned on when the reset signal indicates the reset period, and the second switch is turned off when the reset signal indicates the hold period. ### Claim 4 (depends on 1) The voltage hold circuit according to claim 1, wherein the first hold circuit includes a third switch configured to connect a capacitor to a first current source whose current direction is a first direction in the case where a voltage value of the input voltage signal is smaller than a voltage value held in a capacitor, and the second hold circuit includes a fourth switch configured to connect the capacitor to a second current source whose current direction is a second direction reverse to the first direction in the case where a voltage value of the input voltage signal is larger than a voltage value held in the capacitor. ### Claim 5 (depends on 4) The voltage hold circuit according to claim 4, wherein the first and second current sources are configured by a bidirectional current source whose current direction is reversed between the hold period and the reset period. ### Claim 6 A voltage hold circuit configured to operate every processing cycle, the processing cycle including a hold period and a reset period following the hold period, and hold a voltage value for an input voltage signal, the voltage hold circuit comprising: a generation circuit configured to generate a reset voltage signal which varies according to the input voltage signal; a hold circuit configured to operate to hold a minimum voltage value for the input voltage signal in the hold period every the processing cycle; and a reset circuit configured to reset an output voltage based on the reset voltage signal in the reset period every the processing cycle. ### Claim 7 (depends on 6) The voltage hold circuit according to claim 6, wherein the hold circuit includes a switch configured to connect a capacitor to a reference potential node in the case where a voltage value of the input voltage signal is smaller than a voltage value held in the capacitor. ### Claim 8 A voltage hold circuit configured to hold a voltage value for an input voltage signal, the voltage hold circuit comprising: a determination circuit configured to determine an increase or a decrease in the input voltage signal; a first hold circuit configured to operate to hold a minimum voltage value for the input voltage signal every first period, the determination circuit determining an increase in the input voltage signal in the first period; and a second hold circuit configured to operate to hold a maximum voltage value for the input voltage signal every second period, the determination circuit determining a decrease in the input voltage signal in the second period. ### Claim 9 (depends on 8) The voltage hold circuit according to claim 8, wherein the first hold circuit includes a first switch configured to connect a capacitor to a reference potential node in the case where a voltage value of the input voltage signal is smaller than a voltage value held in the capacitor in the first period, and the second hold circuit includes a second switch configured to connect the capacitor to a power supply voltage node in the case where a voltage value of the input voltage signal is larger than a voltage value held in the capacitor in the second period. ### Claim 10 (depends on 1) A voltage monitoring circuit, comprising: the voltage hold circuit according to claim 1; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 11 (depends on 6) A voltage monitoring circuit, comprising: the voltage hold circuit according to claim 6; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 12 (depends on 8) A voltage monitoring circuit, comprising; the voltage hold circuit according to claim 8; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 13 (depends on 1) A semiconductor integrated circuit, comprising: an internal circuit configured to perform processing based on an input voltage signal; the voltage hold circuit according to claim 1; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 14 (depends on 6) A semiconductor integrated circuit, comprising: an internal circuit configured to perform processing based on an input voltage signal; the voltage hold circuit according to claim 6; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 15 (depends on 8) A semiconductor integrated circuit, comprising: an internal circuit configured to perform processing based on an input voltage signal; the voltage hold circuit according to claim 8; and an analog/digital converter configured to convert a voltage value held in the voltage hold circuit from an analog value to a digital value. ### Claim 16 (depends on 13) The semiconductor integrated circuit according to claim 13, wherein the input voltage signal is a power supply voltage of a power supply voltage node of the internal circuit, the semiconductor integrated circuit further comprising: a logic circuit configured to receive a digital voltage value output by the analog/digital converter and output a control signal for controlling the power supply voltage. ### Claim 17 (depends on 14) The semiconductor integrated circuit according to claim 14, wherein the input voltage signal is a power supply voltage of a power supply voltage node of the internal circuit, the semiconductor integrated circuit further comprising: a logic circuit configured to receive a digital voltage value output by the analog/digital converter and output a control signal for controlling the power supply voltage. ### Claim 18 (depends on 15) The semiconductor integrated circuit according to claim 15, wherein the input voltage signal is a power supply voltage of a power supply voltage node of the internal circuit, the semiconductor integrated circuit further comprising: a logic circuit configured to receive a digital voltage value output by the analog/digital converter and output a control signal for controlling the power supply voltage. ### Claim 19 (depends on 16) The semiconductor integrated circuit according to claim 16, further comprising: a power supply circuit configured to control the power supply voltage supplied to the power supply voltage node of the internal circuit based on the control signal. ### Claim 20 (depends on 17) The semiconductor integrated circuit according to claim 17, further comprising: a power supply circuit configured to control the power supply voltage supplied to the power supply voltage node of the internal circuit based on the control signal. ### Claim 21 (depends on 18) The semiconductor integrated circuit according to claim 18, further comprising: a power supply circuit configured to control the power supply voltage supplied to the power supply voltage node of the internal circuit based on the control signal.