Continuous-time pipelined adcs with event-driven sampling
AssigneesAnalog Devices, Inc., Massachusetts Institute of Technology
InventorsGabriele MANGANARO, Rishabh MITTAL, Hae-Seung LEE
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Abstract
Uniformly-sampled, residue-generating analog-to-digital converters (ADCs), such as uniformly-sampled continuous-time pipelined ADCs, suffer from over-ranging of the residue signal, which can lead to severe signal distortion. Conventionally, power consuming techniques and oversampling are used to address the over-ranging problem. To reduce the range of the residue signal and reduce other impairments, an event-driven sub-quantizer (sub-ADC) and a sub-digital-to-analog converter (sub-DAC) can be implemented in at least one of the stages of the residue-generating ADC, to generate a continuous-time residue signal.
Claims20
A residue-generating analog-to-digital converter (ADC), comprising:
- a first residue-generating stage, comprising:
- a first continuous-time delay circuit to receive an analog input signal and generate a delayed analog input signal;
- a first continuous-time quantizer to receive the analog input signal and generate a continuous-time output signal;
- a first continuous-time digital-to-analog converter (DAC) responsive to the continuous-time output signal;
- a first summing node to receive the delayed analog input signal and an output from the first continuous-time DAC and generate a continuous-time summed signal;
- and
- a first filter to filter the continuous-time summed signal, and generate a continuous-time residue signal;
- and
- a second stage to quantize the continuous-time residue signal.
A continuous-time residue-generating stage for an analog-to-digital converter (ADC), comprising:
- a delay circuit to delay an analog input signal;
- a quantizer to change an output responsive to the analog input signal crossing one of a plurality of reference levels;
- a digital-to-analog converter (DAC) responsive to the output of the quantizer;
- and
- a node to generate a summed signal based on a delayed analog input signal from the delay circuit and an output of the DAC.
A method for preventing over-ranging of a residue signal in a residue-generating analog-to-digital converter (ADC), comprising:
- delaying an analog input signal;
- detecting the analog input signal crossing one of a plurality of reference levels;
- in response to detecting the crossing, changing a level-quantized signal;
- reconstructing the analog input signal based on the level-quantized signal;
- generating and amplifying the residue signal based on a delayed analog input signal and a reconstructed analog input signal;
- and
- quantizing the residue signal.
Dependencies are inferred from the claim text.