System on chip architecture, interposer, fpga and method of design
AssigneeMenta
InventorsVincent MARKUS, Yoan DUPRET
Life of this patent
Estimating the term…
Abstract
A system on chip device, where the active interposer/chassis incorporates an FPGA/eFPGA, may be used to flexibly implement interposer/chassis operations such as a network on chip communication protocols, state machines, interfaces, or data conversion, digital interfaces operations, data filtering operations, data filtering operations, and the like, or any other digital operation as required, so that analogue and mixed signals only need be addressed in dedicated chiplets.
Claims14
A disaggregated system-on-chip device comprising adapted to perform a specified function, said device comprising a plurality of chiplets from a predefined library of chiplets, each said chiplet implementing one or more specified operation and having a predetermined structure, and an active interposer to provide interoperability functions between said chiplets in view of said specified function, characterized in that said active interposer comprises an FPGA.
An active interposer device for use in a disaggregated system-on-chip comprising adapted to perform a specified function, said disaggregated system-on-chip comprising a plurality of chiplets from a predefined library of chiplets, each said chiplet implementing one or more specified operation and having a predetermined structure, said active interposer providing interoperability functions between said chiplets in view of said specified function, characterized in that said active interposer comprises an FPGA.
An FPGA device for use in an active interposer in a disaggregated system-on-chip comprising adapted to perform a specified function, said disaggregated system-on-chip comprising a plurality of chiplets from a predefined library of chiplets, each said chiplet implementing one or more specified operation and having a predetermined structure, said active interposer providing interoperability functions between said chiplets in view of said specified function.
A method of designing a disaggregated system-on-chip device to perform a specified function said method, comprising the steps of selecting a plurality of chiplets from a predefined library of chiplets, each said chiplet implementing one or more specified operation and having a predetermined structure, defining an active interposer to provide interoperability functions between said chiplets in view of said specified function, wherein said step of defining an active interposer comprises configuring an FPGA to perform at least a part of interoperability functions.
A data structure defining an FPGA device for use in an active interposer/chassis in a disaggregated system-on-chip comprising adapted to perform a specified function, said disaggregated system-on-chip comprising a plurality of chiplets from a predefined library of chiplets, each said chiplet implementing one or more specified operation and having a predetermined structure, said active interposer/chassis providing interoperability functions between said chiplets in view of said specified function.
Dependencies are inferred from the claim text.