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US 2022/0209871 A1Published application
Module with high peak bandwidth i/o channels
OwnerL. Pierre de Rochemontinventor
Life of this patent
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Abstract
A high peak bandwidth I/O channel embedded within a multilayer surface interface that forms the bus circuitry electrically interfacing the output or input port on a first semiconductor die with the input or output port on a second semiconductor die.
Claims1
A computing system that comprises one or more hybrid computing modules that further comprise at least one high peak bandwidth I/O channel embedded within a multilayer surface interface, wherein,
- the high peak bandwidth I/O link additionally comprises vias that form an electrical interface with input and output ports on a semiconductor die, a semiconductor carrier, or an interposer circuit embedded within the stacked assembly of semiconductor chips;
- the multilayer surface interface comprises conducting means that forms a channel link within a data signal plane that electrically interfaces signal transmission between the vias, low permittivity/ultra-low loss dielectric, additional conductive means to form power planes and ground planes, and
- the multilayer surface interface further comprises a passive network filtering circuit comprising capacitive, inductive, and resistive elements embedded within the high peak bandwidth I/O channel,
- wherein,
- the passive network filtering circuit further comprises high energy density electroceramic dielectric components that polarize and depolarize with femto-second response times.
2 more elements
Dependencies are inferred from the claim text.