Operational transconductance amplifier circuit including active inductor

A memory device comprising:

• a memory cell array including multiple memory blocks that each include a plurality of memory cells connected to word lines and bit lines arranged in rows and columns, and configured to perform a write operation and a read operation for the plurality of memory cells by using an internal power supply voltage;
• and
• a clock buffer configured to receive a pair of differential input signals having a clock signal and an inverted clock signal and correct a duty cycle of the clock signal,
• wherein the clock buffer comprises:
• an input circuit configured to generate a first differential current and a second differential current based on the clock signal and the inverted clock signal;
• a first current mirror circuit including a first active inductor including a P-channel transistor and configured to generate a first mirror current and a second mirror current based on the first differential current;
• a second current mirror circuit including a second active inductor including a P-channel transistor and configured to generate a third mirror current and a fourth mirror current based on the second differential current;
• a third current mirror circuit including a third active inductor including an N-channel transistor and configured to generate a fifth mirror current based on the third mirror current;
• and
• a fourth current mirror circuit including a fourth active inductor including an N-channel transistor and configured to generate a sixth mirror current based on the second mirror current.