Ternary in-memory accelerator

A circuit of cells used as a memory array and capable of in-memory arithmetic, comprising:

• at least one block of signed ternary processing cells, the at least one block comprising:
• an output;
• and
• a plurality of columns (C1 . . . CN), each column (Ci) comprising:
• a first bitline (BLi),
• a second bitline (BLBi),
• a plurality of signed ternary processing cells (TPC1,Ci . . . TPCL,Ci) coupled to each other in a parallel fashion such that the first bitlines of the plurality of the TPCs in each column are coupled to each other and the second bitlines of the plurality of TPCs in each column are coupled to each other, each signed ternary processing cell comprising:
• a first memory cell, adapted to hold a first digital value;
• a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a weight representing a first signed ternary operand;
• a signed ternary input representing a second signed ternary operand;
• and
• a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand by voltage changes in the first and second bitlines;
• and
• the plurality of columns (C1 . . . CN) form a plurality of rows (R1 . . . RL), each row (Ri) having:
• a first read wordline (WLR1-i),
• a second read wordline (WLR1-i),
• the plurality of signed ternary processing cells (TPCi,C1 . . . TPCi,CN) coupled to each other in a parallel fashion such that the first read wordline of the plurality of the TPCs in each row are coupled to each other and the second read wordline of the plurality of TPCs in each row are coupled to each other,
• at least one sense circuit adapted to (a) receive the coupled first and second bitlines of each column of the plurality of columns, (b) compute the difference between the values represented by the coupled first bitlines and the coupled second bitlines, and (c) output the subtraction result on the output of the at least one block, wherein, the output of the at least one block represents a vector matrix multiplication of an N×L matrix of the first signed ternary operands by L×1 of the second signed ternary operands resulting in the output vector of N×1.