Programmable analog signal processing array for time-discrete processing of analog signals

A programmable analog processing array for programmable time-discrete processing of incoming analog input signals in accordance with a desired signal processing function and for providing processed analog output signals in accordance with the signal processing function, the processing array comprising:

• a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network and that each comprise a set of cell circuit elements formed by
• a switchable clock input port for receiving a clock signal;
• a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal;
• an analog multiplier element receiving the delayed slice input signal, for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, and
• an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal, for providing an analog adder output signal corresponding to a sum of the adder input signals;
• and
• an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal;
• a pre-configurable analog signal bus for receiving and providing the analog input signals to the network of processing slices and for interconnecting any given processing slice to one or more respective other of the processing slices of the network of processing slices to transport the slice input signals and slice output signals;
• a configuration-signal bus for receiving and routing respective configuration control signals to the individual processing slices, wherein the respective configuration control signals are for configuring
• individual time delays of the respective delay elements,
• individual multiplication factors of the respective multiplier elements,
• individual selections of adder input signals to the respective adder elements,
• individual switchable interconnections of the respective processing slices to the analog signal bus for routing, in accordance with a programmable signal-bus configuration and with the signal processing function, the input signals, the respective slice input signals, and the respective slice output signals between the processing slices via the analog signal bus;
• and, connected to the network of processing slices,
• individual switching states of the clock input ports for allowing or blocking the provision of the clock signal to the respective processing slices;
• a configuration control unit for receiving a configuration code and for using the configuration code to generate the configuration control signals to configure the network of processing slices for implementing an analog signal processing circuit that in operation performs the desired signal processing function.