High performance phase locked loop
AssigneeKandou Labs, S.A.
InventorArmin Tajalli
Life of this patent
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Abstract
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
Claims20
A method comprising:
- obtaining at least one phase of a reference signal and at least three phases of a local oscillator signal at an input to a matrix phase comparator of a phase-locked loop (PLL);
- forming at least three partial phase-error signals by comparing a single phase of the at least one phase of the reference signal to corresponding phases of the at least three phases of the local oscillator signal;
- applying a respective weighting factor to each partial phase-error signal of the at least three phase-error signals, wherein the respective weighting factors applied to each partial phase-error signal collectively form a discrete time domain filter weighting configuration that adds at least one of a zero and a pole to a transfer function of the PLL;
- and
- generating a composite phase-error signal by forming a summation of the at least three weighted partial phase-error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase-error signal.
An apparatus comprising:
- a local oscillator configured to generate at least three phases of a local oscillator signal;
- a plurality of partial phase comparators of a phase-locked loop configured to obtain at least one phase of a reference signal and the at least three phases of a local oscillator signal, and to responsively generate a set of at least three weighted partial phase-error signals, each weighted partial phase-error signal generated by:
- forming a comparison of one phase of the at least one phase of the reference signal to a corresponding phase of the at least three phases of the local oscillator signal;
- and
- applying a respective weighting factor to the comparison, wherein the respective weighting factor applied to each comparison collectively form a discrete time domain filter weighting configuration that adds at least one of a zero and a pole to a transfer function of the PLL;
- and
- a summation circuit configured to generate a composite phase-error signal by forming a summation of the at least three weighted partial phase-error signals, and to responsively adjust a fixed phase of the local oscillator using the composite phase-error signal.
Dependencies are inferred from the claim text.