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US 2022/0190844 A1Published application
Method and apparatus to perform cyclic redundancy check training in a memory module
AssigneeIntel Corporation
InventorsTonia M. ROSE, Saravanan SETHURAMAN
Life of this patent
Estimating the term…
Abstract
A differential Data Strobe (DQS) signal is used to transmit and receive Cyclic Redundancy Check (CRC) between a host memory controller and a memory module. The differential DQS strobe signal is trained before it is used for transactions. The training is performed by sending and receiving a CRC pattern on the differential DQS strobe signal between the host memory controller and a buffer in the memory module.
Claims20
A memory module comprising:
- a hardware interface to interface with a command bus and a data bus having multiple data (DQ) signal lines and a CRC signal line, the hardware interface to receive a command on the command bus to trigger training of signaling on the multiple data (DQ) signal lines and the CRC signal line;
- and
- a data buffer to include pattern generation and checking circuitry for each of the multiple data (DQ) signal lines and the CRC signal line to perform training of signaling on the multiple data (DQ) signal lines and the CRC signal line without interfering with data stored in a memory integrated circuit.
A memory controller comprising:
- command logic to generate a command to train signaling on a data bus of a memory module, the data bus having multiple data (DQ) signal lines and a CRC signal line;
- and
- a hardware interface to interface with a command bus, the hardware interface to send the command to the memory module, the memory module comprising a data buffer, the data buffer to include pattern generation and checking circuitry for each of the multiple data (DQ) signal lines and the CRC signal line to perform training of signaling on the multiple data (DQ) signal lines and the CRC signal line without interfering with data stored in a memory integrated circuit.
A system comprising:
- a memory controller;
- and
- a memory module, the memory module comprising:
- a hardware interface to interface with a command bus and a data bus having multiple data (DQ) signal lines and a CRC signal line, the hardware interface to receive a command from the memory controller on the command bus to trigger training of signaling on the multiple data (DQ) signal lines and the CRC signal line;
- and
- a data buffer to include pattern generation and checking circuitry for each of the multiple data (DQ) signal lines and the CRC signal line to perform training of signaling on the multiple data (DQ) signal lines and the CRC signal line without interfering with data stored in a memory integrated circuit.
3 more elements
Dependencies are inferred from the claim text.