Automatic frequency calibration and lock detection circuit and phase locked loop including the same

A phase locked loop comprising:

• an automatic frequency calibration and lock detection circuit configured to generate an automatic frequency calibration output signal and a lock done signal based on a reference frequency signal and an output frequency signal, the automatic frequency calibration output signal representing a result of a first calibration operation on the output frequency signal, the lock done signal representing a completion of a second calibration operation on the output frequency signal;
• a control circuit configured to generate a voltage control signal based on the reference frequency signal and the output frequency signal;
• a capacitor bank array, at least a part of the capacitor bank array being selectively enabled based on the automatic frequency calibration output signal;
• and
• a voltage controlled oscillator (VCO) circuit configured to generate the output frequency signal based on the capacitor bank array and the voltage control signal, and
• wherein the automatic frequency calibration and lock detection circuit includes:
• a frequency error generator circuit configured to generate a frequency error signal based on the reference frequency signal and the output frequency signal, the frequency error signal representing a difference between a frequency of the output frequency signal and a target frequency;
• an automatic frequency calibration signal generator circuit configured to generate the automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal, the automatic frequency calibration done signal representing a completion of the first calibration operation;
• and
• a lock flag generator circuit configured to generate the lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal, and
• wherein the frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.

An automatic frequency calibration and lock detection circuit comprising:

• a frequency counter circuit configured to generate a frequency count signal and a frequency threshold signal based on a reference frequency signal, an output frequency signal, a first division control signal and a second division control signal, the frequency count signal representing a count value for the output frequency signal, the frequency threshold signal representing a target frequency;
• a digital comparator circuit configured to generate a frequency error signal by comparing the frequency count signal with the frequency threshold signal, the frequency error signal representing a difference between a frequency of the output frequency signal and the target frequency;
• an automatic frequency calibration signal generator circuit configured to generate an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal, the automatic frequency calibration output signal representing a result of a first calibration operation on the output frequency signal, the automatic frequency calibration done signal representing a completion of the first calibration operation;
• a lock flag generator circuit configured to generate a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal, the lock done signal representing a completion of a second calibration operation on the output frequency signal;
• and
• a timing generator circuit configured to generate the first clock signal, the second clock signal and the first division control signal,
• wherein, during a first operation phase in which the first calibration operation is performed, the automatic frequency calibration signal generator circuit is enabled and the lock flag generator circuit is disabled,
• wherein, during a second operation phase in which the second calibration operation is performed subsequent to the first operation phase, the automatic frequency calibration signal generator circuit is disabled and the lock flag generator circuit is enabled,
• wherein the frequency counter circuit is configured to generate a divided reference frequency signal by dividing the reference frequency signal based on the first division control signal, and to generate the frequency count signal by counting the frequency of the output frequency signal based on the divided reference frequency signal, and
• wherein a frequency threshold value that is included in the frequency threshold signal and corresponds to the target frequency is determined based on the first division control signal and the second division control signal.