Phase interpolation-based fractional-n sampling phase-locked loop

A phase-locked loop (PLL), comprising:

• a phase-frequency detector (PFD) configured to produce a PFD output corresponding to a phase error between a reference clock signal and a feedback signal;
• a phase interpolation-based sampler configured to produce a positive slope signal and a negative slope signal in response to the PFD output, the phase interpolation-based sampler further configured to set the positive and negative slope signals to a first slope in response to an edge of the feedback signal and to set the positive and negative slope signals to a second slope in response to an edge of a delayed feedback signal, the phase interpolation-based sampler further configured to determine the first slope in response to a quantization error correction indication, the phase interpolation-based sampler further configured to sample the positive slope signal to produce a positive sampled slope signal and to sample the negative slope signal to produce a negative sampled slope signal;
• a transconductance cell configured to produce a current signal in response to a difference between the positive sampled slope signal and the negative sampled slope signal;
• a filter configured to produce a frequency control signal in response to the current signal produced by the transconductance cell;
• a voltage-controlled oscillator (VCO) configured to produce a VCO output signal in response to the frequency control signal;
• and
• a fractional frequency divider circuit configured to divide a frequency of the VCO output signal to produce the feedback signal, and to determine the quantization error correction indication, wherein the quantization error correction indication is based on a quantization error introduced by fractional division of the VCO output signal.

A method for operating a phase-locked loop (PLL), comprising:

• producing, by a phase-frequency detector (PFD), a PFD output corresponding to a phase error between a reference clock signal and a feedback signal;
• producing, by a phase interpolation-based sampler, a slope signal in response to the PFD output;
• adjusting, by the phase interpolation-based sampler, the slope signal in response to a quantization error correction indication;
• sampling the slope signal by the phase interpolation-based sampler;
• filtering a sampled slope signal produced by the phase interpolation-based sampler to produce a frequency control signal;
• producing, by a voltage-controlled oscillator (VCO), a VCO output signal in response to the frequency control signal;
• producing the feedback signal by a fractional frequency divider circuit dividing a frequency of the VCO output signal;
• and
• determining, by the fractional frequency divider circuit, the quantization error correction indication, wherein the quantization error correction indication is based on a quantization error introduced by fractional division of the VCO output signal.

A phase-locked loop (PLL) apparatus, comprising:

• means for producing a phase-frequency detection output corresponding to a phase error between a reference clock signal and a feedback signal;
• means for producing a slope signal in response to the phase-frequency detection output;
• means for adjusting the slope signal in response to a quantization error correction indication;
• means for sampling the slope signal;
• means for filtering a sampled slope signal to produce a frequency control signal;
• means for producing a voltage-controlled oscillator (VCO) output signal in response to the frequency control signal;
• means for fractionally dividing a frequency of the VCO output signal to produce the feedback signal;
• and
• means for determining the quantization error correction indication, wherein the quantization error correction indication is based on a quantization error introduced by the means for fractionally dividing.