Hybrid power stage and gate driver circuit

A power semiconductor switching stage comprising:

• a hybrid power semiconductor switching device comprising:
• a high-side switch and a low-side switch connected in a half-bridge configuration, wherein:
• the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein each power transistor of the high-side switch is a GaN power transistor;
• the low-side switch is a Silicon (Si) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein each power transistor of the low-side switch is a Si MOSFET;
• a gate driver comprising a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver;
• a gate drive output of the low-side driver being connected to a gate of each Si MOSFET through a first gate drive circuit comprising a gate resistor to provide a gate drive of a first voltage range for driving the plurality of Si MOSFETs;
• a gate drive output of the high-side driver being connected to a gate of each GaN power transistor through a second gate drive circuit comprising a gate resistor and a level shift circuit to provide a gate drive of a second voltage range, different from the first voltage range, for driving the plurality of GaN power transistors.

A power semiconductor switching stage comprising:

• a hybrid power semiconductor switching device comprising:
• a high-side switch and a low-side switch connected in a half-bridge configuration, wherein:
• the high-side switch is implemented with one transistor or a plurality of transistors, wherein each transistor of the high-side switch is a GaN power transistor;
• and
• the low-side switch is implemented with one transistor or a plurality of transistors, wherein each transistor of the low-side switch is a Si MOSFET;
• a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver;
• a gate drive output of the low-side driver being connected to a gate of each Si MOSFET of the low-side switch through a first gate drive circuit comprising a first gate resistor to provide a gate drive of a first voltage range for driving each Si MOSFET;
• a gate drive output of the high-side driver being connected to a gate of each GaN power transistor of the high-side switch through a second gate drive circuit comprising a second gate resistor and a level shift circuit to provide a gate drive of a second voltage range for driving each GaN power transistor;
• wherein for a supply voltage VDD, said first voltage range for driving each Si MOSFET is in a range from 0V to VDD, and the second voltage range for driving each GaN power transistor is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.