US 2022/0190814 A1 · PHASE INTERPOLATOR AND CLOCK SIGNAL SELECTOR THEREOF

Abstract

A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.

Claims11

Dependent claims

A clock signal selector, comprising:

a selector, receiving a plurality of clock signals with different phases, wherein the selector selects one of the clock signals according to a selection signal to generate a selected clock signal;
and
a selection signal generator, coupled to the selector, and generating the selection signal,
wherein, when the selector switches from selecting a first clock signal as the selected clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.

1 more element

A phase interpolator, comprising:

selectors of N stages, wherein each of the selectors of N stages receives a plurality of clock signals with different phases, each of the selectors of N stages receives N selection signals, each of the selectors of N stages generates selected clock signals of N stages with different phases according to the N selection signals, and N is an integer greater than 1, wherein a phase of the selected clock signal of an ith stage is ahead of a phase of the selected clock signal of an (i+1)th stage, and i is a positive integer less than N;
a selection signal generator, adapted for generating the N selection signals, wherein the selection signal generator generates the selection signal of the ith stage according to the selected clock signal of an (i+M)th stage, and M is greater than or equal to 1;
and
an interpolation calculation circuit, executing an interpolation operation on two of the selected clock signals of N stages to generate an output clock signal.

1 more element

Dependencies are inferred from the claim text.

Phase interpolator and clock signal selector thereof

Life of this patent

Phase interpolator and clock signal selector thereof

Life of this patent

Abstract

Claims11