US 2022/0190719 A1 · Power Converter Control

Abstract

Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

Claims15

Dependent claims

A controller for a power converter controlled by a pulse-wide modulation (PWM) control signal, the controller including:

(a) a counter having a clock signal input, inputs for receiving signals corresponding to at least one feedback voltage and signals indicating a count direction, and an output for providing an M-bit count value in response to the received signals;
(b) a digital-to-analog converter coupled to the output of the counter and outputting a signal corresponding to the provided M-bit count value to generate the PWM control signal;
(c) a clock signal selector, coupled to the clock signal input of the counter and configured to be coupled to a first clock signal and to a second clock signal, the second clock signal having a higher frequency than the first clock signal;
and
(d) an under-regulation detector circuit, configured to be coupled to the at least one feedback voltage, the under-regulation detector circuit outputting an under-regulation signal to the clock signal selector if the at least one feedback voltage is less than an under-regulation reference voltage;
wherein while the under-regulation detector circuit outputs the under-regulation signal, the clock signal selector couples the second clock signal to the clock signal input of the counter, and otherwise couples the first clock signal to the clock signal input of the counter.

3 more elements

A power converter including:

(a) a DC-to-DC converter circuit having an input for receiving an input voltage, and an output for outputting an output voltage different from the input voltage in response to a pulse-width modulated (PWM) control signal;
(b) a PWM duty cycle controller coupled to the DC-to-DC converter circuit and configured to generate the PWM control signal to the DC-to-DC converter circuit from an M-bit count value;
(c) a counter having a clock signal input, inputs for receiving signals corresponding to at least one feedback voltage and indicating a count direction, and an output providing the M-bit count value;
(d) a digital-to-analog converter configured to output to the PWM duty cycle controller a signal corresponding to the provided M-bit count value from the counter;
(e) a first detector configured to be coupled to the at least one feedback voltage, the first detector circuit outputting a first control signal to the counter if the at least one feedback voltage is greater than a first reference voltage;
(f) a second detector circuit configured to be coupled to the at least one feedback voltage, the second detector circuit outputting a second control signal if the at least one feedback voltage is less than a second reference voltage;
(g) a clock signal selector, coupled to the clock signal input of the counter and configured to be coupled to a first clock signal and to a second clock signal, the second clock signal having a higher frequency than the first clock signal;
and
(h) an under-regulation detector circuit, coupled to the clock signal selector, to an under-regulation reference voltage, and configured to be coupled to the at least one feedback voltage, the under-regulation detector circuit outputting an under-regulation signal to the clock signal selector if the at least one feedback voltage is less than the under-regulation reference voltage;
wherein while the under-regulation detector circuit outputs the under-regulation signal, the clock signal selector couples the second clock signal to the clock signal input of the counter, and otherwise couples the first clock signal to the clock signal input of the counter.

7 more elements

Dependencies are inferred from the claim text.

Power Converter Control

Life of this patent

Power Converter Control

Life of this patent

Abstract

Claims15