Resistive random-access memory (rram) cell with recessed bottom electrode sidewalls

An integrated circuit (IC) comprising a memory cell, wherein the memory cell comprises:

• a lower electrode;
• a data storage layer overlying the lower electrode, wherein the data storage layer has plasma etch damage extending laterally into the data storage layer from a storage sidewall of the data storage layer toward a center of the data storage layer, and wherein the plasma etch damage extends laterally into the data storage layer from the storage sidewall by a damage distance;
• and
• an upper electrode overlying the data storage layer;
• wherein a difference between a width of the lower electrode and a width of the data storage layer is greater than or equal to about two times the damage distance.

An integrated circuit (IC) comprising a memory cell, wherein the memory cell comprises:

• a first electrode;
• a second electrode;
• and
• a data storage layer having a first region with a threshold amount of crystalline damage and further having a second region without the threshold amount of crystalline damage;
• wherein the first electrode, the second electrode, and the data storage layer are vertically stacked with the data storage layer between the first and second electrodes, and wherein the first and second electrodes are configured to generate an electric field across the data storage layer with comparatively low and high electric field strengths respectively at the first and second regions.