In-memory resistive random access memory xor logic using complimentary switching

A method, comprising:

• providing a resistive random access memory (RRAM) gate comprising:
• a first electrode;
• a second electrode;
• switching layer comprising a dielectric material;
• and
• a complimentary switching (CS) mitigation layer comprising a material having a CS k-value that is lower than a k-value of the switching layer and a CS thermal conductivity that is higher than a thermal conductivity of the switching layer;
• resetting the RRAM gate by supplying a Vreset voltage pulse;
• performing a logic operation by supplying the first electrode with a first bias and the second electrode with a second bias, wherein the first bias comprises a selection from the group consisting of zero voltage and a positive complimentary switching voltage (Vset), and the second bias comprises a selection from the group consisting of zero voltage and negative Vset;
• and
• sensing a bias state of the RRAM gate using a sensing voltage that is lower than Vset, wherein a Vset voltage from the first electrode alone or the second electrode alone results in a bias state equal to 1, and a Vset voltage from both the first electrode and the second electrode or a zero voltage from the first electrode and the second electrode results in a bias state equal to 0.