Back to results
US 2022/0190236 A1Published application
Semiconductor structure, memory cell and memory array
AssigneeChangxin Memory Technologies, Inc.
InventorsBaolei WU, Xiaoguang WANG, Yulei WU
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.
Claims20
A semiconductor structure, comprising:
- active regions that are separate from one another and located on a substrate;
- connecting pads, wherein each of the connecting pads comprises a first part and a second part, each of the first part and the second part is connected to end parts of respective adjacent ones of the active regions, the first part extends in a first direction, and the second part extends in a second direction;
- and
- magnetic tunnel junctions (MTJs), wherein each of the MTJs is connected to a respective one of the connecting pads.
1 more element
A memory cell, comprising:
- a transistor, and
- a memory structure,
- wherein one end of the transistor is connected to one end of the memory structure;
- and
- the other end of the transistor, a gate electrode of the transistor, the other end of the memory structure, and the end of the transistor connected to the memory structure are respectively used as a first end, a second end, a third end and a fourth end of the memory cell.
2 more elements
A memory array, comprising:
- M*N memory cells forming an array of M rows and N columns, wherein both M and the N are positive integers greater than or equal to 2, and each memory cell comprises a transistor and a memory structure, one end of the transistor is connected to one end of the memory structure, and the other end of the transistor, a gate electrode of the transistor, the other end of the memory structure, and the end of the transistor connected to the memory structure are respectively used as a first end, a second end, a third end and a fourth end of the memory cell;
- M bit lines in one-to-one correspondence to the M rows of memory cells, wherein third ends of memory cells in each of the M rows are all connected to a corresponding one of the M bit lines;
- and
- N word lines in one-to-one correspondence to the N columns of memory cells, wherein second ends of memory cells in each of the N columns are all connected to a corresponding one of the N word lines, wherein a fourth end of a memory cell in an Xth row and Yth column is connected to a fourth end of a memory cell in a Pth row a Qth column, X is equal to P minus A, and Y is equal to Q minus B.
1 more element
Dependencies are inferred from the claim text.