US 2022/0190184 A1 · INTEGRATED CIRCUIT COMPRISING A SINGLE PHOTON AVALANCHE DIODE AND CORRESPONDING MANUFACTURING METHOD

Abstract

A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

Claims12

Dependent claims

An integrated circuit, comprising:

a semiconductor well doped with a first type of dopant;
and
a single photon avalanche diode (SPAD) in the semiconductor well, said SPAD including a PN junction between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant;
wherein the first doped region has a shape that incorporates local variations in dopant concentration that are configured to generate, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, a monotonic variation in electrostatic potential between the first doped region and the semiconductor well.

1 more element

A method for manufacturing an integrated circuit including a single photon avalanche diode (SPAD), comprising:

implanting a first region doped with a first type of dopant in a semiconductor well doped with the first type of dopant;
implanting a second region doped with a second type of dopant opposite to the first type of dopant in the semiconductor well;
wherein the first and second regions form a PN junction of the SPAD;
and
wherein implanting the first doped region comprises forming local variations in dopant concentration that are configured to generate, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/546,503Filed 9 Dec 2021

Priority

FR 201299910 Dec 2020

Published

16 Jun 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10F 30/225
The devices having only one potential barrier, e.g. photodiodes: the potential barrier working in avalanche mode, e.g. avalanche photodiodes
H10F 71/00
Manufacture or treatment of devices covered by this subclass
H10F 77/148
Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies: shapes of potential…
H10F
Solar cells and light sensors

Integrated circuit comprising a single photon avalanche diode and corresponding manufacturing method

Life of this patent

Integrated circuit comprising a single photon avalanche diode and corresponding manufacturing method

Life of this patent

Abstract

Claims12