Strained vertical channel semiconductor device, method of manufacturing the same, and electronic apparatus including the same
AssigneeInstitute of Microelectronics, Chinese Academy of Sciences
InventorHuilong Zhu
Life of this patent
Estimating the term…
Abstract
A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.
Claims29
A method of manufacturing a semiconductor device, comprising:
- providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side in the lateral direction, wherein the second side is opposite to the first side;
- replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer;
- and
- replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.
A semiconductor device, comprising:
- a vertical channel portion on a substrate;
- source and drain portions located at an upper end of the channel portion and a lower end of the channel portion relative to the substrate;
- and
- a first gate stack on a first side of the channel portion in a lateral direction, and a second gate stack on a second side of the channel portion in the lateral direction, wherein the second side is opposite to the first side,
- wherein a first gate dielectric layer in the first gate stack partially overlaps with a second gate dielectric layer in the second gate stack.
Dependencies are inferred from the claim text.