Ncfets with complimentary capacitance matching using stacked n-type and p-type nanosheets

2:

• The method according to claim 1, wherein the NCFET device includes a shared internal gate between the first FET and the second FET.

3:

• The method according to claim 1, wherein the NCFET device has a complimentary logic circuit.

4:

• The method according to claim 1, wherein the ferroelectric layer comprises HfO2 E and is formed in a recess of the work function metal layer.

5:

• The method according to claim 1, further comprising forming an insulating layer between the first FET and the second FET.

6:

• The method according to claim 1,
• wherein the first FET is a PFET including a pWF metal layer stack and the second FET is an NFET including an nWF metal layer stack, and
• wherein a portion of the pWF metal layer stack contacts the nWF metal layer stack at a boundary between the PFET region and the NFET region.

7:

• The method according to claim 1, wherein the first FET is a PFET including a pWF metal layer stack and the second FET is an NFET including an nWF metal layer stack, and
• wherein the pWF metal layer stack is formed on top of the nWF metal layer stack.

8:

• The method according to claim 1, wherein the first FET is a PFET including a pWF metal layer stack and the second FET is an NFET including an nWF metal layer stack, and
• wherein the nWF metal layer stack is formed on top of the pWF metal layer stack.

9:

• The method according to claim 1, wherein the dielectric interfacial layer directly contacts the first FET.

10:

• The method according to claim 1, wherein the dielectric interfacial layer directly contacts the second FET.

12:

• The NCFET device according to claim 11, wherein the NCFET device includes a shared internal gate between the first FET and the second FET.

13:

• The NCFET device according to claim 11, wherein the NCFET device has a complimentary logic circuit.

14:

• The NCFET device according to claim 11, wherein the ferroelectric layer comprises HfO2 and is formed in a recess of the work function metal layer.

15:

• The NCFET device according to claim 11, further comprising an insulating layer between the first FET and the second FET.

16:

• The NCFET device according to claim 11, wherein the first FET is a PFET region including a pWF metal layer stack and the second FET is an NFET region including an nWF metal layer stack, and
• wherein a portion of the pWF metal layer stack contacts the nWF metal layer stack at a boundary between the PFET region and the NFET region.

17:

• The NCFET device according to claim 11, wherein the first FET is a PFET including a pWF metal layer stack and the second FET is an NFET region including an nWF metal layer stack, and
• wherein the pWF metal layer stack is formed on top of the nWF metal layer stack.

18:

• The NCFET device according to claim 11, wherein the first FET is a PFET including a pWF metal layer stack and the second FET is an NFET region including an nWF metal layer stack, and
• wherein the nWF metal layer stack is formed on top of the pWF metal layer stack.

19:

• The NCFET device according to claim 11, wherein the dielectric interfacial layer directly contacts the first FET.

20:

• The NCFET device according to claim 11, wherein the dielectric interfacial layer directly contacts the second FET.