Semiconductor device structure with inner spacer

A semiconductor device structure, comprising:

• a substrate;
• a first nanostructure over the substrate;
• a second nanostructure over the first nanostructure, wherein the substrate, the first nanostructure, and the second nanostructure are spaced apart from each other;
• a gate stack wrapping around the first nanostructure and the second nanostructure;
• a first inner spacer between the substrate and the first nanostructure;
• a first low dielectric constant structure between the substrate and the first nanostructure, wherein the first low dielectric constant structure has a first taper end;
• a second inner spacer between the first nanostructure and the second nanostructure;
• and
• a second low dielectric constant structure between the first nanostructure and the second nanostructure, wherein the second low dielectric constant structure has a second taper end.

A semiconductor device structure, comprising:

• a substrate;
• a first nanostructure over the substrate;
• a second nanostructure over the first nanostructure;
• a gate stack wrapping around the first nanostructure and the second nanostructure;
• a first inner spacer between the substrate and the first nanostructure;
• a first low dielectric constant structure between the substrate and the first nanostructure, wherein the first low dielectric constant structure has a first width;
• a second inner spacer between the first nanostructure and the second nanostructure;
• and
• a second low dielectric constant structure between the first nanostructure and the second nanostructure, wherein the second low dielectric constant structure has a second width, and the first width is different from the second width in a cross-sectional view of the first low dielectric constant structure and the second low dielectric constant structure.