Integrated circuit structures having gesnb source or drain structures

A method of fabricating an integrated circuit structure, the method comprising:

• forming a vertical arrangement of horizontal nanowires;
• forming a gate stack around the vertical arrangement of horizontal nanowires;
• removing a portion of the vertical arrangement of horizontal nanowires in source or drain regions to expose a first end and a second end of the vertical arrangement of horizontal nanowires;
• forming a first epitaxial source or drain structure at the first end of the vertical arrangement of horizontal nanowires;
• and
• forming a second epitaxial source or drain structure at the second end of the vertical arrangement of horizontal nanowires, wherein the first and second epitaxial source or drain structures comprise germanium, tin and boron.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a vertical arrangement of horizontal nanowires;
• a gate stack around the vertical arrangement of horizontal nanowires;
• a first epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires;
• and
• a second epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires, wherein the first and second epitaxial source or drain structures comprise germanium, tin and boron.