Reduction of bottom epitaxy parasitics for vertical transport field effect transistors

A method of forming a semiconductor device structure, the method comprising:

• forming a sacrificial layer within a lower portion of a source/drain region disposed within a substrate of a vertical transport field effect transistor structure, the sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with the substrate;
• forming a source/drain layer within an upper portion of the source/drain region above the sacrificial layer;
• removing the sacrificial layer thereby forming a cavity between the substrate and the source/drain layer;
• forming a first layer within the cavity;
• and
• forming a second layer, wherein the second layer is encapsulated by the first layer.

A method of forming a semiconductor device structure, the method comprising:

• forming a sacrificial layer within a lower portion of a source/drain region disposed within a substrate of a vertical transport field effect transistor structure;
• forming a source/drain layer within an upper portion of the source/drain region above the sacrificial layer;
• removing the sacrificial layer thereby forming a cavity between the substrate and the source/drain layer;
• and
• forming an insulating layer within the cavity.