Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungseok HA, Gukil AN, Keun Hwi CHO, Sungmin KIM
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Abstract
Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.
Claims20
A semiconductor device comprising:
- a substrate including an active pattern;
- a device isolation layer on the substrate and in a trench that defines the active pattern;
- a plurality of semiconductor patterns that are stacked on the active pattern and are spaced apart from each other in a vertical direction;
- a plurality of ferroelectric patterns on the plurality of semiconductor patterns, respectively;
- and
- a gate electrode on the plurality of ferroelectric patterns,
- wherein, in a cross-sectional view taken along a longitudinal direction of the gate electrode:
- the plurality of ferroelectric patterns are spaced apart from each other in the vertical direction,
- each of the plurality of ferroelectric patterns is between the gate electrode and a respective one of the plurality of semiconductor patterns,
- each of the plurality of ferroelectric patterns surrounds a respective one of the plurality of semiconductor patterns, and
- the gate electrode includes a work function metal pattern that in a space between adjacent ones of the plurality of ferroelectric patterns.
A semiconductor device comprising:
- a substrate including an active pattern;
- a device isolation layer on the substrate and in a trench that defines the active pattern;
- first, second and third semiconductor patterns that are sequentially stacked on the active pattern and spaced apart from each other in a vertical direction;
- a source/drain pattern connected to the first, second and third semiconductor patterns;
- a first ferroelectric pattern between the active pattern and the first semiconductor pattern, a second ferroelectric pattern between the first semiconductor pattern and the second semiconductor pattern, and a third ferroelectric pattern between the second semiconductor pattern and the third semiconductor pattern;
- a gate electrode on the first, second and third ferroelectric patterns;
- and
- first, second and third inner spacers between the source/drain pattern and the first, second and third ferroelectric patterns, respectively,
- wherein the first, second and third ferroelectric patterns directly contact the first, second and third inner spacers, respectively.
A semiconductor device comprising:
- a substrate including a first active pattern and a second active pattern;
- a device isolation layer on the substrate and in a trench that is between the first and second active patterns;
- a plurality of first semiconductor patterns that are stacked on the first active pattern and spaced apart from each other in a vertical direction;
- a first source/drain pattern connected to the plurality of first semiconductor patterns;
- a plurality of second semiconductor patterns that are stacked on the second active pattern and spaced apart from each other in the vertical direction;
- a second source/drain pattern connected to the plurality of second semiconductor patterns;
- a first ferroelectric pattern on the plurality of first semiconductor patterns;
- a second ferroelectric pattern on the plurality of second semiconductor patterns;
- an inner spacer between the second ferroelectric pattern and the second source/drain pattern;
- and
- a gate electrode on the first ferroelectric pattern and the second ferroelectric pattern,
- wherein the first ferroelectric pattern directly contacts the first source/drain pattern, and
- wherein the second ferroelectric pattern is spaced apart from the second source/drain pattern by the inner spacer.
Dependencies are inferred from the claim text.