Nonvolatile memory device and nonvolatile memory system including the same

A nonvolatile memory device comprising:

• a peripheral logic structure including a peripheral circuit on a substrate;
• a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure;
• a first stacked structure including a first conductive film stacked on the horizontal semiconductor layer in a direction perpendicular to the substrate;
• a pass transistor configured to apply an operating voltage to the first conductive film and disposed in the peripheral logic structure;
• and
• a control transistor connected to a source/drain of the pass transistor,
• wherein the peripheral circuit includes control logic configured to control the operating voltage and the control logic includes the control transistor,
• wherein the control transistor and the pass transistor are connected through a lower interconnection structure which is disposed under the upper surface of the peripheral logic structure.

A nonvolatile memory system comprising:

• a main board;
• a nonvolatile memory device disposed on the main board;
• and
• a controller disposed on the main board and electrically connected to the nonvolatile memory device,
• wherein the nonvolatile memory device includes:
• a peripheral logic structure including a peripheral circuit on a substrate;
• a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure;
• a plurality of stacked structures arranged in a first direction on the horizontal semiconductor layer and including a plurality of interlayer insulating films and a plurality of conductive films alternately stacked in a direction perpendicular to the substrate;
• a first opening disposed between two adjacent stacked structures of the plurality of stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure;
• and
• a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening, and
• wherein the peripheral logic structure includes control logic with a control transistor overlapping a region defined by the second opening in a plan view and the control logic is configured to control operation of the plurality of stacked structures.