Alignment-Tolerant Gallium Oxide Device

An electronic circuit including a gallium oxide power field effect transistor (FET), the gallium oxide field effect transistor comprising:

• a base layer;
• a doped gallium oxide channel layer disposed on top of the base layer;
• a dielectric barrier layer disposed on top of the gallium oxide channel layer, wherein a portion of the dielectric layer is altered for providing a source contact or a drain contact;
• the source contacts disposed on top of the altered dielectric barrier layer;
• the drain contacts disposed on top of the altered dielectric barrier layer, with one each of the drain contacts disposed in an interdigitated manner between adjacent ones of the source contacts such that channels are defined as odd channels and with even channels disposed therebetween;
• and
• gate contacts disposed on top of the dielectric barrier layer in of the odd channels or the even channels while the even channels or the odd channels without gate contacts are electrically insulated,
• wherein misalignment of the gate contacts in the odd channels between source contacts and the drain contacts causes odd channels to turn on at a rate and voltage that differs from a turn on rate and voltage resulting from misalignment of the gate contacts in the event channels between drain contacts and source contacts and wherein having removing the gate contacts from the odd channels or the even channels provides uniform turn on rate and voltage.