Vertical mosfet having trench gate structure containing silicon carbide

A vertical metal oxide semiconductor field effect transistor (MOSFET) containing silicon carbide and having a pn junction interface through which a current passes in a forward direction, the vertical MOSFET comprising:

• a starting substrate of a first conductivity type, having a first surface and a second surface opposite to each other;
• a first first-conductivity-type epitaxial layer containing silicon carbide;
• a second first-conductivity-type epitaxial layer containing silicon carbide, provided on the first surface of the starting substrate via the first first-conductivity-type epitaxial layer, the second first-conductivity-type epitaxial layer containing silicon carbide having an impurity concentration lower than an impurity concentration of the starting substrate and an impurity concentration of the first first-conductivity-type epitaxial layer, the second first-conductivity-type epitaxial layer further containing, as an impurity thereof, a first element that is a dopant of the first conductivity type;
• a first semiconductor region of the first conductivity type, provided as a portion of the second first-conductivity-type epitaxial layer, in contact with the first first-conductivity-type epitaxial layer, the first semiconductor region having, as an impurity thereof, the first element and a second element, the second element forming recombination centers;
• a second-conductivity-type epitaxial layer containing silicon carbide, the second-conductivity-type epitaxial layer forming the pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer that includes the first semiconductor region;
• a plurality of second semiconductor regions of the first conductivity type, selectively provided in the second-conductivity-type epitaxial layer;
• a plurality of trenches that penetrate through the plurality of second semiconductor regions, respectively, and through the second-conductivity-type epitaxial layer, and reach the second first-conductivity-type epitaxial layer;
• a plurality of gate electrodes that are provided in the plurality of trenches via a plurality of gate insulating films, respectively;
• a first electrode electrically connected to the second semiconductor regions and the second-conductivity-type epitaxial layer;
• and
• a second electrode electrically connected to the second surface of the starting substrate, wherein
• a lifetime of the minority carrier of the first semiconductor region is shorter than a lifetime of the minority carrier of another portion of the second first-conductivity-type epitaxial layer excluding the first semiconductor region, and
• a concentration of the second element in the first semiconductor region is at most 1/10 of a concentration of the first element in the second first-conductivity-type epitaxial layer.