Transistor with air gap under source/drain region in bulk semiconductor substrate

A transistor, comprising:

• a bulk semiconductor substrate;
• a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region;
• a first air gap defined in the bulk semiconductor substrate and in direct contact with the first source/drain region;
• a second air gap defined in the bulk semiconductor substrate and in direct contact with the second source/drain region;
• a gate over the channel region;
• and
• a doped polysilicon isolation region in the bulk semiconductor substrate extending below the gate, the first source/drain region, the second source/drain region, the first air gap and the second air gap,
• wherein the first air gap and the second air gap each have a substantially rectangular cross-sectional shape, and a spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region.

A method, comprising:

• forming a first silicon-germanium (SiGe) section and a second SiGe section spaced from the first SiGe section on a bulk semiconductor substrate;
• forming a silicon layer over the first SiGe section and the second SiGe section;
• forming a first source/drain region in the silicon layer and a second source/drain region in the silicon layer;
• forming a gate over a channel region between the first source/drain region and the second source/drain region;
• and
• forming a first air gap under the first source/drain region and a second air gap under the second source/drain region by removing the first SiGe section and the second SiGe section from under the silicon layer,
• wherein a spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the air gaps are not under the channel region.