Deck select transistor for three-dimensional cross point memory

A method of fabricating a deck select transistor, the method comprising:

• forming a conductive via above a substrate;
• forming an interconnect line structure above and coupled with the via, wherein the via is coupled with a first portion of the line structure;
• oxidizing a second portion of the line structure;
• depositing a channel material on a sidewall adjacent to the second portion of the line structure;
• depositing a gate oxide layer on the channel material;
• and
• forming a gate electrode on the gate oxide layer.

A system comprising:

• a processor;
• and
• a memory device structure comprising:
• a first plurality of line structures, wherein individual ones of the first plurality of line structures each comprise a first transistor channel;
• a second plurality of line structures substantially orthogonal to the first plurality of line structures, wherein individual ones of the second plurality of line structures each comprise a second transistor channel;
• a memory cell at each cross-point between the first plurality of line structures and the second plurality of line structures;
• and
• a plurality of terminal interconnects wherein individual ones of the plurality of terminal interconnects are coupled between individual ones of the line structures and individual ones of a plurality of logic transistors, and wherein individual ones of the transistor channels are between the individual ones of the terminal interconnects and the memory cells.