Pillar select transistor for 3-dimensional cross point memory

A method of fabricating a vertical transistor, comprising:

• forming a first electrode structure above a substrate;
• forming a material layer stack on the first electrode structure, wherein forming the structure comprises depositing a gate electrode material on a first dielectric above the first electrode, and depositing a second dielectric on the gate electrode material;
• forming an opening in the material layer stack and exposing the first electrode;
• forming a gate dielectric layer in the opening adjacent the gate electrode material;
• forming a channel layer in the opening adjacent the gate dielectric layer;
• forming a second dielectric in the opening adjacent the channel layer, wherein the dielectric partially fills the opening;
• and
• forming a second electrode in the opening.

A system comprising:

• a battery to power the system;
• and
• a memory device structure, comprising:
• a transistor, comprising:
• a channel between a source and a drain, the channel along a longitudinal axis of the transistor;
• a gate electrode along a first direction orthogonal to the longitudinal axis;
• and
• a gate dielectric layer between the gate electrode and the channel;
• a first interconnect coupled with the source or the drain, the first interconnect colinear with the channel;
• a pair of second interconnects along a second direction orthogonal to both the longitudinal axis and the first direction;
• and
• a pair of memory cells, wherein individual ones of the pair of memory cells comprises a selector element and a memory element, wherein a first terminal of the individual ones of the pair of memory cells is coupled to the first interconnect and wherein a second terminal of the individual ones of the pair of memory cells is coupled to individual ones of the pair of second interconnects.