Tier architecture for 3-dimensional cross point memory

A method of fabricating a memory device, comprising:

• forming a plurality of openings in a material layer stack comprising a plurality of bilayers, wherein each of the plurality of bilayers comprises a first dielectric above a second dielectric;
• laterally recessing a portion of the second dielectric within the plurality of openings to form lateral recesses;
• forming layers of a selector element within the lateral recesses;
• forming layers of a memory element within the lateral recesses adjacent to the selector element;
• etching layers of the memory element and of the selector element to isolate a plurality of memory cells, each of the memory cells comprising one of the memory elements adjacent to one of the selector elements;
• and
• forming electrodes adjacent to the plurality of memory cells.

A system comprising:

• a processor;
• and
• a memory device, comprising:
• a plurality of memory cells, wherein individual ones of the plurality comprise a selector element in series with a non-volatile memory element between a first terminal and a second terminal;
• a pair of first conductors within a first tier, wherein individual ones of the first conductors are coupled to the first terminal of a first adjacent pair of memory cells in a first row orthogonal to the first conductors;
• a pair of second conductors within a second tier and parallel to the first conductors, wherein individual ones of the second conductors are coupled to the first terminal of a second adjacent pair of memory cells in a second row, below the first row;
• and
• a third conductor that extends between the first and second tiers, wherein the third conductor is between each of the pair of the first conductors and the pair of the second conductors, and is coupled to second terminals of both the first and second adjacent pairs of memory cells.