Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines

A method used in forming an array of capacitors, comprising:

• forming a vertical stack comprising insulating material directly above conducting material;
• forming pillars above the vertical stack and that individually comprise first capacitor electrode material aside insulator material;
• forming a first lining comprising a capacitor insulator and a second lining comprising a second capacitor electrode material in space that is laterally-between immediately-adjacent of the pillars to less-than-fill such space;
• using opposing sidewalls of the second lining to comprise a mask while etching through:
• (a) bottoms of the first and second linings that are laterally-between the opposing sidewalls of the first and second linings, and (b) the insulating material to the conducting material there-below;
• and
• after the etching, forming conductor material directly against the opposing sidewalls of the second lining and directly against the conducting material to directly electrically couple together the opposing sidewalls of the second lining and the conducting material;
• individual of the capacitors comprising the first capacitor electrode material of individual of the pillars, the capacitor insulator, the second capacitor electrode material, and the conductor material.

A method used in forming an array of memory cells, comprising:

• forming a vertical stack comprising transistor material directly above insulator material directly above insulating material directly above conducting material;
• forming pillars above the insulating material, the pillars comprising the transistor material and first capacitor electrode material;
• forming a first lining comprising a capacitor insulator and a second lining comprising a second capacitor electrode material in space that is laterally-between immediately-adjacent of the pillars to less-than-fill such space;
• using opposing sidewalls of the second lining to comprise a mask while etching through:
• (a) bottoms of the first and second linings that are laterally-between the opposing sidewalls of the second lining, and (b) the insulating material to the conducting material there-below;
• after the etching, forming conductor material directly against the opposing sidewalls of the second lining and directly against the conducting material to directly electrically couple together the opposing sidewalls of the second lining and the conducting material;
• individual of the capacitors comprising the first capacitor electrode material of individual of the pillars, the capacitor insulator, the second capacitor electrode material, and the conductor material;
• and
• forming vertical transistors above the capacitors and that individually comprise the transistor material of the individual pillars.

An array of capacitors comprising:

• insulating material directly above conducting material;
• a plurality of capacitors individually comprising a first capacitor electrode, a second capacitor electrode laterally-outward of the first capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode;
• and
• a plurality of conductive lines that are individually longitudinally-elongated horizontally and extend alongside and are directly against the capacitor insulator, individual of the conductive lines comprising the second capacitor electrode of individual of the capacitors, the individual conductive lines comprising a shared of the second capacitor electrodes of immediately-laterally-adjacent of the capacitors and interconnecting the individual second capacitor electrodes longitudinally along the individual conductive lines, the individual conductive lines comprising an upper part that is wider than a lower part in a vertical cross-section laterally through that individual conductive line, the lower part extending through the insulating material and being directly against the conducting material.

An array of memory cells comprising:

• insulating material directly above conducting material;
• a plurality of capacitors above the insulating material in rows along a row direction and in columns along a column direction;
• the capacitors individually comprising a first capacitor electrode, a second capacitor electrode laterally-outward of the first capacitor electrode, and a capacitor insulator between the first and second capacitor electrode;
• a plurality of vertical transistors in the rows and columns above the plurality of capacitors;
• the vertical transistors individually comprising a top source/drain region, a bottom source/drain region, and a channel region vertically there-between;
• individual of the vertical transistors being directly electrically coupled to individual of the first capacitor electrodes, a plurality of gate lines that are individually laterally-proximate the channel regions along individual of the rows;
• a plurality of digitlines that are individually above the gate lines and electrically coupled to the top source/drain regions along individual of the columns;
• and
• a plurality of conductive lines that are individually longitudinally-elongated in and extend along the row direction aside and are directly against the capacitor insulator and that are below the gate lines, individual of the conductive lines comprising the second capacitor electrode of individual of the capacitors, the individual conductive lines comprising a shared of the second capacitor electrodes of immediately-row-adjacent of the capacitors and interconnecting the individual second capacitor electrodes longitudinally along immediately-adjacent of the rows, the individual conductive lines comprising an upper part that is wider than a lower part in a vertical cross-section laterally through that individual conductive line, the lower part extending through the insulating material and being directly against the conducting material.