Multibit ferroelectric memory cells and methods for forming the same

A method of forming a semiconductor structure, comprising:

• forming multiple repetitions of a unit layer stack over a substrate, the unit layer stack comprising an insulating layer, a first-type sacrificial material layer comprising a first sacrificial material, and a second-type sacrificial material layer comprising a second sacrificial material different from the first sacrificial material;
• forming memory openings through the multiple repetitions of the unit layer stack;
• forming first memory recesses by isotropically recessing instances of the first-type sacrificial material layers around the memory openings;
• forming first ferroelectric material portions in the first memory recesses;
• forming second memory recesses by isotropically recessing instances of the second-type sacrificial material layers around the memory openings;
• forming second ferroelectric material portions in the second memory recesses, wherein ferroelectric memory elements including a respective one of the first ferroelectric material portions and a respective one of the second ferroelectric material portions are formed;
• and
• forming vertical semiconductor channels in the memory openings on a respective vertical stack of the ferroelectric memory elements.

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers;
• and
• memory stack structures vertically extending through the alternating stack, wherein:
• each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers;
• and
• each of the ferroelectric memory elements comprises a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness,
• wherein:
• one of an outer sidewall of the first ferroelectric material portion and an outer sidewall of the second ferroelectric material portion contacts a respective one of the electrically conductive layers;
• and
• another of the outer sidewall of the first ferroelectric material portion and the outer sidewall of the second ferroelectric material portion is laterally spaced from the respective one of the electrically conductive layers by a dielectric liner.