Three-dimensional memory devices and methods for forming the same

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a peripheral circuit;
• and
• a second semiconductor structure coupled to the first semiconductor structure, comprising:
• a memory stack comprising interleaved conductive layers and dielectric layers;
• a plurality of channel structures each extending through the memory stack and electrically connected to the peripheral circuit;
• a plurality of slit structures each extending through the memory stack and laterally separating the plurality of channel structures into a plurality of blocks;
• a semiconductor layer comprising a plurality of first doped regions each in contact with a respective one of the plurality of slit structures, and a plurality of second doped regions in contact with the plurality of first doped regions;
• a plurality of insulating structures each extending from a backside of the semiconductor layer to a respective one of the plurality of first doped regions to separate the plurality of second doped regions into the blocks;
• and
• a plurality of contacts each in contact with a respective one of the second doped regions.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming, from a first side of a substrate, a doped area in the substrate;
• forming a plurality of channel structures each extending through a memory stack at the first side of the substrate;
• forming a first doped region in the substrate and in contact with the doped area;
• forming a slit structure extending through the memory stack to the first doped region, and laterally separating the plurality of channel structures into a plurality of blocks;
• forming a plurality of first contacts each in contact with the doped area;
• and
• forming an insulating structure extending from a second side of the substrate to the first doped region to separate the doped area into a plurality of second doped regions.