3d memory semiconductor devices and structures with bit-line pillars

A 3D memory device, the device comprising:

• a plurality of memory cells,
• wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
• wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
• and
• a plurality of bit-line pillars,
• wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
• wherein said plurality of bit-line pillars are vertically oriented,
• wherein said channel is horizontally oriented,
• wherein a plurality of said channels has been recrystallized, and
• wherein said recrystallized was initiated from said source and/or said drain.

A 3D memory device, the device comprising:

• a plurality of memory cells,
• wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
• wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
• and
• a plurality of bit-line pillars,
• wherein each bit-line pillar of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
• wherein said bit-line pillars are vertically oriented, and
• wherein said channel is horizontally oriented;
• and
• a memory controller circuit,
• wherein said memory controller circuit is capable of providing a word-line hold voltage, and
• wherein said word-line hold voltage extends retention of said plurality of memory cells.